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information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a admc401 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 rev. b single-chip, dsp-based high performance motor controller functional block diagram arithmetic units shifter mac alu memory sport 1 interval timer dm ram 1k 16 pm rom 2k 24 pm ram 2k 24 interrupt controller encoder interface 8 channel 12-bit adc 26 mips dsp core serial ports program sequencer data address generators dag 1 dag 2 program memory address data memory address program memory data data memory data sport 0 watch- dog timer event capture unit digital i/o unit external address bus external data bus precision voltage reference 16-bit pwm generation power- on reset motor control peripherals 2 channel auxiliary pwm features 26 mips fixed-point dsp core single cycle instruction execution (38.5 ns) adsp-21xx family code compatible 16-bit arithmetic and logic unit (alu) single cycle 16-bit 16-bit multiply and accumulate into 40-bit accumulator (mac) 32-bit shifter (logical and arithmetic) multifunction instructions single cycle context switch zero overhead looping conditional instruction execution two independent data address generators memory configuration 2k 24-bit internal program memory ram 2k 24-bit internal program memory rom 1k 16-bit internal data memory ram 14-bit address bus and 24-bit data bus for external memory expansion high resolution multichannel adc 12-bit pipeline flash analog-to-digital converter eight dedicated analog inputs simultaneous sampling capability all eight inputs converted in <2 s 4.0 v p-p input voltage range pwm synchronized or external convert start internal or external voltage reference out-of-range detection voltage reference internal 2.0 v 2.0% voltage reference three-phase 16-bit pwm generation unit programmable switching frequency, dead time and minimum pulsewidth edge resolution of 38.5 ns one or two updates per switching period hardware polarity control individual enable/disable of each output high frequency chopping mode dedicated shutdown pin ( pwmtrip ) additional shutdown pins in i/o system high output sink and source capability (10 ma) incremental encoder interface unit quadrature rates to 17.3 mhz programmable filtering of encoder inputs alternative frequency and direction mode two registration inputs to latch count value optional hardware reset of counter single north marker mode count error monitor function dedicated 16-bit loop timer (periodic interrupts) companion encoder event (1/t) timer (continued on page 14)
recommended operating conditions b grade parameter min max unit v dd digital supply voltage 4.75 5.25 v av dd analog supply voltage 4.75 5.25 v t amb ambient operating temperature C40 +85 c electrical characteristics parameter test conditions min max unit v ih hi-level input voltage 1, 2, 3 @ v dd = max 2.0 v v il lo-level input voltage 1, 2, 3 @ v dd = min 0.8 v v oh hi-level output voltage 1, 3, 4, 5, 6 @ v dd = min, i oh = C1.0 ma 2.4 v @ v dd = min, i oh = C0.1 ma v dd C 0.3 v v ol lo-level output voltage 1, 3, 4, 5, 6 @ v dd = min, i ol = 2.0 ma 0.4 v v oh hi-level output voltage 5 @ v dd = min, i oh = C10.0 ma 2.4 v v ol lo-level output voltage 5 @ v dd = min, i ol = 10.0 ma 1.2 v i ih hi-level input current 7 @ v dd = max, v in = v dd max 10 a i ih hi-level input current 8 @ v dd = max, v in = v dd max 100 a i ih hi-level input current 9 @ v dd = max, v in = v dd max 10 a i il lo-level input current 7 @ v dd = max, v in = 0 v 10 a i il lo-level input current 8 @ v dd = max, v in = 0 v 10 a i il lo-level input current 9 @ v dd = max, v in = 0 v 100 a i ozh hi-level three-state leakage current 10 @ v dd = max, v in = v dd max 10 a i ozl lo-level three-state leakage current 10 @ v dd = max, v in = 0 v 10 a i dd digital supply current (idle) 11 @ v dd = max 40 ma i dd digital supply current (dynamic) 12 @ v dd = max 110 ma i dd analog supply current @ av dd = max 60 ma c i input pin capacitance 13 v in = 2.5 v, f in = 1 mhz, 8 pf t amb = +25 c c o output pin capacitance 13, 14 v in = 2.5 v, f in = 1 mhz, 8 pf t amb = +25 c notes 1 bidirectional pins: d0Cd23, rfs0, rfs1, tfs0, tfs1, sclk0 and sclk1, pio0Cpio11. 2 input only pins: pwmtrip , pwmpol, pwmsr , reset , eia, eib, eiz, eis, etu0, etu1, dr1a, dr1b, dr0, clkin, convst, mmap, bmode, br and pwd . 3 programmable i/o pins (pio0Cpio11). 4 output pins: pwmsync, aux0, aux1, clkout, dt0, dt1, bg , bgh , pms , dms , bms , rd , wr , pwdack and a0Ca13. 5 output pins: ah, al, bh, bl, ch and cl. 6 although specified for ttl outputs, all admc401 outputs are cmos-compatible and will drive to v dd C0.3 v and gnd+0.3 v assuming no dc loads. 7 input only pins reset , eia, eib, eiz, eis, etu0, etu1, dr1a, dr1b, dr0, clkin, convst, mmap, bmode, br and pwd . 8 input pins with internal pull-down pio0Cpio11 and pwmtrip . 9 input pins with internal pull-up, pwmpol and pwmsr . 10 three-statable pins: a0Ca13, d0Cd23, pms , dms , bms , rd , wr , dt0, dt1, rfs0, rfs1, tfs0, tfs1, sclk0, sclk1. 11 idle refers execution of the idle instruction. deasserted pins are driven to v dd or gnd. current reflects device operation with clkout disabled. 12 current reflects device operating with no output loads. 13 guaranteed but not tested. 14 output pin capacitance is the capacitive load for any three-state output pin. specifications subject to change without notice. (v dd = av dd = 5 v 5%, gnd = agnd = 0 v, t amb = ?0 c to +85 c, clkin = 13 mhz, unless otherwise noted) rev. b C2C admc401?pecifications
analog-to-digital converter parameter test conditions min typ max unit ac specifications snr signal to noise ratio f in = 1.0 khz 68 70 db snrd signal to noise and distortion f in = 1.0 khz 66 69 db thd total harmonic distortion f in = 1.0 khz C76 C70 db ctlk channel-channel crosstalk f in = 1.0 khz C89 C72 db cmrr common-mode rejection ratio C90 C72 db psrr power supply rejection ratio 0.025 0.1 % fsr accuracy inl integral nonlinearity 0.6 1.5 lsb dnl differential nonlinearity 0.5 1.0 lsb no missing codes 12 bits guaranteed zero error 0.1 0.25 % fsr gain error 1 0.4 1.0 % fsr temperature drift zero error 0.025 % fsr gain error 1 0.025 % fsr input voltage v in voltage span 4.0 v p-p c in input capacitance 2 10 pf conversion time t conv total conversion time all 8 channels 1.88 s notes 1 excludes internal voltage reference error. 2 analog input pins vin0 to vin7. typical values are neither tested nor guaranteed. specifications subject to change without notice. voltage reference parameter test conditions min typ max unit v ref output voltage reference sense = refcom 1.96 2.0 2.04 v output voltage tolerance 1 sense = refcom 6 mv output current 1.0 ma load regulation 1.0 ma load current 0.3 1.5 mv power supply rejection ratio 0.1 1.5 mv reference input resistance 8 k ? notes 1 relative tolerance due to temperature change, t min to t max . specifications subject to change without notice. power-on reset parameter test conditions min typ max unit v rst reset threshold voltage 3.25 4.0 v v hyst hysteresis voltage 75 mv specifications subject to change without notice. (v dd = av dd = 5 v 5%, gnd = agnd = 0 v, t amb = ?0 c to +85 c, clkin = 13 mhz, vin0 to vin7 = 4.0 v p-p, v ref = 2.0 v, unless otherwise noted) (v dd = av dd = 5 v 5%, gnd = agnd = 0 v, t amb = ?0 c to +85 c, clkin = 13 mhz, vin0 to vin7 = 4.0 v p-p, v ref = 2.0 v, unless otherwise noted) (gnd = agnd = 0 v, t amb = ?0 c to +85 c, clkin = 13 mhz, unless otherwise noted) admc401 C3C rev. b
rev. b admc401 C4C absolute maximum ratings* supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v input voltage . . . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v output voltage swing . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v operating temperature range (ambient) . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c lead temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . +280 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stresses only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the admc401 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ordering guide temperature instruction package package model range rate description option admc401bst C40 c to +85 c 26 mhz 144-lead plastic thin quad flatpack (lqfp) st-144 admc401-advevalkit development tool kit ADMC401-PB evaluation/processor board timing parameters general notes use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. consequently, you cannot meaningfully add up parameters to derive longer times. timing notes switching characteristics specify how the processor changes its signals. you have no control over this timing; it is dependent on the internal design. timing requirements apply to signals that are controlled outside the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with another device. switching characteristics tell you what the device will do under a given circumstance. also, use the switching characteristics to ensure any timing requirement of a device connected to the processor (such as memory) is satisfied. memory requirements this chart links common memory device specification names and admc401 timing parameters for your convenience. common parameter memory device name function specification name t asw a0Ca13, dms , pms address setup to setup before wr low write start t aw a0Ca13, dms , pms address setup to before wr deasserted write end t wra a0Ca13, dms , pms address hold time hold after wr deasserted t dw data setup before wr high data setup time t dh data hold after wr high data hold time t rdd rd low to data valid oe to data valid t aa a0Ca13, dms , pms , address access time bms to data valid
admc401 C5C rev. b parameter min max unit clock signals t ck is defined as 0.5t cki. the admc401 uses an input clock with a frequency equal to half the instruction rate; a 13 mhz clock (which is equivalent to 76.9 ns) yields a 38.5 ns processor cycle (equivalent to 26 mhz). t ck values within the range of 0.5t cki period should be substituted for all relevant timing parameters to obtain specification value. example: t ckh = 0.5t ck C 10 ns = 0.5 (38.5 ns) C 10 ns = 9.25 ns. timing requirements: t cki clkin period 76.9 150 ns t ckil clkin width low 20 ns t ckih clkin width high 20 ns switching characteristics: t ckl clkout width low 0.5t ck C 10 ns t ckh clkout width high 0.5t ck C 10 ns t ckoh clkin high to clkout high 0 20 ns control signals timing requirement: t rsp reset width low 5t ck 1 ns pwm shutdown signals timing requirements: t pwmtpw pwmtrip width low t ck ns t piopwm pio width low 2t ck ns adc signals t iming requirements: t csi internal convert start width high 2t ck ns t cse external convert start width high 2t ck ns note 1 applies after power-up sequence is complete. internal phase lock loop requires no more than 2000 clkin cycles assuming stable c lkin (not including crystal oscillator start-up time). clkin clkout t ckoh t cki t ckih t ckil t ckh t ckl figure 1. clock signals
rev. b admc401 C6C parameter min max unit interrupts and flags timing requirements : t ifs irqx or fi setup before clkout low 1, 2, 3 0.25t ck + 15 ns t ifh irqx or fi hold after clkout high 1, 2, 3 0.25t ck ns switching characteristics : t foh flag output hold after clkout low 4 0.5t ck C 7 ns t fod flag output delay from clkout low 4 0.5t ck + 5 ns notes 1 if irqx and fi inputs meet t ifs and t ifh setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the following cycle. (refer to interrupt controller operation in the program control chapter of the adsp-2100 family users manual, third edition for further information on interrupt servicing.) 2 edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced. 3 irqx = irq0 and irq1 . 4 flag output = fl1 and fo. clkout flag outputs irq x fi t foh t ifh t ifs t fod figure 2. interrupts and flags
admc401 C7C rev. b parameter min max unit bus request/grant timing requirements : t bh br hold after clkout high 1 0.25t ck +2 ns t bs br setup before clkout low 1 0.25t ck + 17 ns switching characteristics : t sd clkout high to dms , pms , bms , 0.25t ck + 10 ns rd , wr disable t sdb dms , pms , bms , rd , wr disable to bg low 0 ns t se bg high to dms , pms , bms , rd , wr enable 0 ns t sec dms , pms , bms , rd , wr enable to clkout high 0.25t ck C 7 ns t sdbh dms , pms , bms , rd , wr disable to bgh low 2 0ns t seh bgh high to dms , pms , bms , rd , wr enable 2 0ns notes 1 br is an asynchronous signal. if br meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recogniz ed on the following cycle. refer to the adsp-2100 family users manual, third edition for br / bg cycle relationships. 2 bgh is asserted when the bus is granted and the processor requires control of the bus to continue. br clkout pms , dms bms , rd wr bg clkout bgh t bh t bs t sd t sdb t sdbh t seh t se t sec figure 3. bus requestCbus grant
rev. b admc401 C8C parameter min max unit memory read timing requirements : t rdd rd low to data valid 0.5t ck C 11 + w ns t aa a0Ca13, pms , dms , bms to data valid 0.75t ck C 12 + w ns t rdh data hold from rd high 0 ns switching characteristics : t rp rd pulsewidth 0.5t ck C 5 + w ns t crd clkout high to rd low 0.25t ck C 5 0.25t ck + 7 ns t asr a0Ca13, pms , dms , bms setup before rd low 0.25t ck C 6 ns t rda a0Ca13, pms , dms , bms hold after rd deasserted 0.25t ck C 3 ns t rwr rd high to rd or wr low 0.5t ck C 5 ns w = wait states t ck . clkout a0?13 d rd wr dms , pms bms t rwr t rp t asr t crd t aa t rda t rdd t rdh figure 4. memory read
admc401 C9C rev. b parameter min max unit memory write switching characteristics : t dw data setup before wr high 0.5t ck C 7 + w ns t dh data hold after wr high 0.25t ck C 2 ns t wp wr pulsewidth 0.5t ck C 5 + w ns t wde wr low to data enabled 0 ns t asw a0Ca13, dms , pms setup before wr low 0.25t ck C 6 ns t ddr data disable before wr or rd low 0.25t ck C 6 ns t cwr clkout high to wr low 0.25t ck C 5 0.25t ck + 7 ns t aw a0Ca13, dms , pms , setup before wr deasserted 0.75t ck C 9 + w ns t wra a0Ca13, dms , pms hold after wr deasserted 0.25t ck C 3 ns t wwr wr high to rd or wr low 0.5t ck C 5 ns w = wait states t ck . clkout a0 a13 d wr dms , pms rd t wra t wwr t wp t asw t aw t dh t ddr t cwr t wde t dw figure 5. memory write
rev. b admc401 C10C parameter min max unit serial ports timing requirements : t sck sclk period 50 ns t scs dr/tfs/rfs setup before sclk low 5 ns t sch dr/tfs/rfs hold after sclk low 10 ns t scp sclk in width 20 ns switching characteristics : t cc clkout high to sclk out 0.25t ck 0.25t ck + 15 ns t scde sclk high to dt enable 0 ns t scdv sclk high to dt valid 20 ns t rh tfs/rfs out hold after sclk high 0 ns t rd tfs/rfs out delay from sclk high 20 ns t scdh dt hold after sclk high 0 ns t tde tfs(alt) to dt enable 0 ns t tdv tfs(alt) to dt valid 20 ns t scdd sclk high to dt disable 20 ns t rdv rfs (multichannel, frame delay zero) to dt valid 20 ns clkout sclk tfs rfs dr rfs in tfs in dt alternate frame mode rfs out tfs out multichannel mode, frame delay 0 ( mfd = 0 ) t cc t cc t scs t scs t sck t scp t scp t rd t rh t scdv t scde t tde t tdv t rdv t scdh t scdd figure 6. serial ports
admc401 C11C rev. b power dissipation to determine total power dissipation in a specific application, the following equation should be applied for each output: c v dd 2 f c = load capacitance, f = output switching frequency. example: in an application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: assumptions: ? external data memory is accessed every cycle with 50% of the address pins switching. ? external data memory writes occur every other cycle with 50% of the data pins switching. ? each address and data pin has a 10 pf total load at the pin. ? the application operates at v dd = 5.0 v and t ck = 38.5 ns. total power dissipation = p int + (c v dd 2 f ) p int = v dd ( i dd digital + i dd analog ) ( c v dd 2 f ) is calculated for each output: # of pins c v dd 2 f address, dms 8 10 pf 5 2 v 26 mhz = 52.00 mw data output, wr 9 10 pf 5 2 v 13 mhz = 29.25 mw rd 1 10 pf 5 2 v 13 mhz = 3.25 mw clkout 1 10 pf 5 2 v 26 mhz = 6.50 mw 91.00 mw total power dissipation for this example is p int + 91 mw. test conditions output disable time output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. the out- put disable time (t dis ) is the difference of t measured and t decay , as shown in the output enable/disable diagram. the time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 v from the measured output high or low voltage. the decay time, t decay , is dependent on the capacitative load, c l , and the cur- rent load, i l , on the output pin. it can be approximated by the following equation: t cv i decay l l = 05 . from which tt t dis measured decay =? is calculated. if multiple pins (such as the data bus) are dis- abled, the measurement value is that of the last pin to stop driving. 3.0v 1.5v 0.0v 2.0v 1.5v 0.3v input output figure 7. voltage reference levels for ac measure- ments (except output enable/disable) output enable time output pins are considered to be enabled when that have made a transition from a high-impedance state to when they start driving. the output enable time (t ena ) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the output enable/disable diagram. if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. 2.0v 1.0v t ena reference signal output t decay v oh (measured) output stops driving output starts driving t dis t measured v ol (measured) v oh (measured) 0.5v v ol (measured) +0.5v high-impedance state. test conditions cause this voltage level to be approximately 1.5v. v oh (measured) v ol (measured) figure 8. output enable/disable to output pin 50pf +1.5v i oh i ol figure 9. equivalent device loading for ac measure- ments (including all fixtures)
rev. b admc401 C12C pin function description pin pin pin pin pin pin pin pin no. name no. name no. name no. name 1 a9 37 rfs1/ irq0 / srom 73 gnd 109 convst 2 a8 38 tfs1/ irq1 74 d10 110 gnd 3 a7 39 sclk1 75 d9 111 vdd 4 a6 40 dr0 76 d8 112 gnd 5 vdd 41 dt0 77 d7 113 avdd 6 a5 42 rfs0 78 d6 114 avss 7 a4 43 tfs0 79 d5 115 vin7 8 a3 44 sclk0 80 d4 116 v ref 9 gnd 45 vdd 81 d3 117 vin6 10 a2 46 gnd 82 gnd 118 refcom 11 a1 47 pwmtrip 83 d2 119 vin5 12 a0 48 pwmsync 84 d1 120 capt 13 pwd 49 cl 85 d0 121 vin4 14 pwdack 50 ch 86 p11 122 bshan 15 br 51 vdd 87 p10 123 ashan 16 nc 52 gnd 88 p9 124 vin0 17 nc 53 bl 89 p8 125 capb 18 bmode 54 bh 90 vdd 126 vin1 19 mmap 55 al 91 gnd 127 cml 20 vdd 56 ah 92 p7 128 vin2 21 gnd 57 bgh 93 p6 129 gain 22 pwmsr 58 d23 94 p5 130 vin3 23 por 59 d22 95 p4 131 sense 24 reset 60 d21 96 p3 132 avss 25 gnd 61 d20 97 p2 133 avdd 26 gnd 62 d19 98 gnd 134 bms 27 gnd 63 gnd 99 p1 135 pms 28 pwmpol 64 d18 100 p0 136 dms 29 clkin 65 d17 101 aux1 137 rd 30 xtal 66 d16 102 aux0 138 gnd 31 clkout 67 d15 103 etu1 139 bg 32 vdd 68 d14 104 etu0 140 wr 33 gnd 69 d13 105 eis 141 a13 34 dr1a/fi 70 d12 106 eiz 142 a12 35 drib/fi 71 vdd 107 eib 143 a11 36 dt1/fo 72 d11 108 eia 144 a10 nc: these pins must be left unconnected
admc401 C13C rev. b pin configuration a9 a8 a7 a6 vdd a5 a4 a3 gnd a2 a1 a0 pwd pwdack br nc nc bmode mmap vdd gnd pwmsr por reset gnd gnd gnd pwmpol clkin xtal clkout vdd gnd dr1a/f1 dr1b/fi dt1/fo p1 gnd p2 p3 p4 p5 p6 p7 gnd vdd p8 p9 p10 p11 d0 d1 d2 gnd d3 d4 d5 d6 d7 d8 d9 d10 gnd eia eib eiz eis etu0 etu1 aux0 aux1 p0 d11 vdd d12 d13 d14 d15 d16 d17 d18 gnd d19 d20 d21 d22 d23 bgh ah al bh bl gnd vdd ch cl pwmsync pwmtrip gnd vdd sclk0 tfs0 rfs0 dt0 dr0 sclk1 tfs1/ irq1 rfs1/i rq0 / srom convst gnd vdd gnd avdd avss vin7 v ref vin6 refcom vin5 capt vin4 bshan ashan vin0 capb vin1 cml vin2 gain vin3 sense avss avdd bms pms dms rd gnd bg wr a13 a12 a11 a10 nc = no connect pin 1 identifier top view (not to scale) admc401 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 99 98 97 96 95 94 93 92 91 108 107 106 105 104 103 102 101 100 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
rev. b admc401 C14C (continued from page 1) programmable digital i/o (pio) port 12-pin configurable digital i/o port flexible interrupt generation four dedicated pio interrupt vectors each i/o line configurable as pwm shutdown two 8-bit auxiliary pwm outputs programmable switching frequency independent or offset modes two-channel event timer (capture) unit configurable event definition single-shot or free-running modes peripheral interrupt controller manages peripheral interrupts 16-bit watchdog timer internal power-on reset system programmable 16-bit interval timer with prescaler two double buffered synchronous serial ports boot load protocols via sport1: synchronous e 2 prom/srom booting uart boot loader with autobaud synchronous master or slave boot loader debugger interface via sport1: uart interface with autobaud synchronous master or slave interface full debugger for program development industrial temperature range C40 c to +85 c operating voltage 5.0 v 5% package: 144-lead lqfp general description the admc401 is a single-chip dsp-based controller, suitable for high performance control of ac induction motors (acim), permanent magnet synchronous motors (pmsm), brushless dc motors (bdcm) and switched reluctance (sr) motors in indus- trial applications. the admc401 integrates a 26 mips, fixed- point dsp core with a complete set of motor control peripherals that permits fast motor control in a highly integrated environment. the dsp core of the admc401 is the adsp-2171 which is completely code compatible with the adsp-21xx dsp family (as well as other members of the integrated motor controllers of the admc3xx family) and combines three computational units, data address generators and a program sequencer. the computa- tional units comprise an alu, a multiplier/accumulator (mac) and a barrel shifter. the dsp core also adds instructions for bit manipulation, squaring ( x 2 ), biased rounding and global inter- rupt masking. in addition, two flexible double-buffered, bidirec- tional synchronous serial ports are included in the admc401. the admc401 provides 2k 24-bit internal program memory ram, 2k 24-bit internal program memory rom and 1k 16-bit internal data memory ram. the program and data memory ram can be boot loaded through the serial port from either a serial e 2 prom, through a uart connection (either from external host microprocessor or from the motion control debugger) or via a synchronous serial interface from a host microprocessor. alternatively, the internal program and data memory ram may be booted from an external device across the address and data buses. the program memory rom includes a monitor that adds software debugging features through the serial port. additionally, the admc401 device adds significant external memory and peripheral expansion capabilities by making avail- able the full address and data bus of the dsp core. this feature permits expansion of both external program and data memory and means that the dsp core can address up to 14k 24 bits of external program memory and up to 13k 16 bits of external data memory. the admc401 contains a number of special purpose, motor control peripherals. the first is a high performance, 8-channel, 12-bit adc system with dual channel simultaneous sampling ability across 4 pair of inputs. an internal precision voltage refer- ence is also available as part of the adc system. in addition, a three-phase, 16-bit, center-based pwm generation unit can be used to produce high-accuracy pwm signals with minimal pro- cessor overhead. the admc401 also contains a flexible incre- mental encoder interface unit for position sensor feedback; two adjustable -frequency auxiliary pwm outputs, 12 lines of digital i/o; a 2-channel event capture system; a 16-bit watchdog timer; two 16-bit interval timers (one of which can be linked to the encoder interface unit) and an interrupt controller that man- ages all peripheral interrupts. finally, the admc401 contains an integrated power-on-reset (por) circuit that can be used to generate the required reset signal for the device on power-on.
admc401 C15C rev. b bus exchange data address generator #2 data address generator #1 14 14 24 16 6 r bus 16 companding circuitry dma bus pma bus dmd bus pmd bus program sequencer instruction register input regs output regs shifter input regs output regs mac input regs output regs alu serial port 0 receive reg transmit reg control logic dm ram 1k 16 pm rom 2k 24 pm ram 2k 24 serial port 1 receive reg transmit reg 5 timer boot address generator 14 24 2 power down control logic external data bus external address bus figure 10. dsp core block diagram architecture overview figure 10 is a functional block diagram of the dsp core of the admc401. the dsp core is based on the fixed-point adsp- 2171 core that is a member of the fixed-point adsp-21xx family of general purpose dsps from analog devices inc. the adsp -2171 flexible architecture and comprehensive in- struction set allow the processor to perform multiple operations in parallel. in one processor cycle (38.5 ns with a 13 mhz crystal) the dsp core can: ? generate the next program address. ? fetch the next instruction. ? perform one or two data moves. ? update one or two data address pointers. ? perform a computational operation. this all takes place while the admc401 continues to: ? receive and transmit through the serial ports. ? decrement the interval timers. ? generate pwm signals. ? convert the adc input signals. ? operate the encoder interface unit. ? operate all other peripherals including the auxiliary pwm and event timer subsystem. the processor contains three independent computational units: the arithmetic and logic unit (alu), the multiplier/accumulator (mac) and the shifter. the computational units process 16-bit data directly and have provisions to support multiprecision computations. the alu performs a standard set of arithmetic and logic operations; division primitives are also supported. the mac performs single-cycle multiply, multiply/add, multiply/ subtract operations with 40 bits of accumulation. the shifter performs logical and arithmetic shifts, normalization, denormal- ization and derive exponent operations. the shifter can be used to implement numeric format control efficiently, including floating-point representations. the internal result (r) bus di- rectly connects the computational units so that the output of any unit may be the input of any unit on the next cycle. a powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these compu- tational units. the sequencer supports conditional jumps, sub- routine calls and returns in a single cycle. with internal loop counters and loop stacks, the admc401 executes looping code with zero overhead; no explicit jump instructions are required to maintain the loop.
rev. b admc401 C16C two data address generators (dags) provide addresses for simultaneous dual operand fetches from data memory and pro- gram memory. each dag maintains and updates four address pointers (i registers). whenever the pointer is used to access data (indirect addressing), it is post-modified by the value in one of four modify (m) registers. a length value may be associ- ated with each pointer (l registers) to implement automatic modulo addressing for circular buffers. the circular buffering feature is also used by the serial ports for automatic data trans- fers to and from on-chip memory. dag1 generates only data memory addresses but provides an optional bit-reversal capabil- ity. dag2 may generate either program or data memory ad- dresses, but has no bit-reversal capability. efficient data transfer is achieved with the use of five internal buses: ? program memory address (pma) bus. ? program memory data (pmd) bus. ? data memory address (dma) bus. ? data memory data (dmd) bus. ? result (r) bus. program memory can store both instructions and data, permit- ting the admc401 to fetch two operands in a single cycle, one from internal program memory and one from internal data memory. the admc401 can fetch an operand from on-chip program memory and the next instruction in the same cycle. the admc401 writes data from its 16-bit registers to the 24- bit program memory using the px register to provide the lower eight bits. when it reads data (not instructions) from 24-bit program memory to a 16-bit data register, the lower eight bits are placed in the px register. the admc401 can respond to a number of distinct dsp core and peripheral interrupts. the dsp core interrupts include serial port receive and transmit interrupts, timer interrupts, software interrupts and external interrupts. in addition, there is a master reset signal. the motor control peripherals also produce interrupts to the dsp core. the two serial ports (sports) provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed and unframed data transmit and receive modes of operation. each sport can generate an internal programmable serial clock or accept an external serial clock. boot loading of both the program and data memory ram of the admc401 can be through the serial port sport1. alterna- tively the admc401 can be boot loaded from an external byte- wide memory connected to the external address and data buses. after reset, seven wait states are automatically generated. this permits, for example, a 38.5 ns admc401 to use an external 250 ns eprom as boot memory. the internal boot address generator provides the addresses for booting from an external byte-wide memory. a programmable interval counter is also included in the dsp core and can be used to generate periodic interrupts. a 16-bit count register (tcount) is decremented every n processor cycles, where n-1 is a scaling value stored in the 8-bit tscale register. when the value of the counter reaches zero, an inter- rupt is generated and the count register is reloaded from a 16- bit period register (tperiod). the admc401 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. each instruction is executed in a single 38.5 ns processor cycle (for a 13 mhz crystal). the admc401 assem- bly language uses an algebraic syntax for ease of coding and readability. a comprehensive set of development tools supports program development. serial ports the admc401 incorporates two complete synchronous serial ports (sport0 and sport1) for serial communications and multiprocessor communication. the following is a brief list of the capabilities of the admc401 sports. refer to the adsp- 2100 family users manual, third edition for further details. ? sports are bidirectional and have a separate, double- buffered transmit and receive section. ? sports can use an external serial clock or generate their own serial clock internally. ? sports have independent framing for the receive and trans- mit sections. sections run in a frameless mode or with frame synchronization signals internally or externally generated. frame synchronization signals are active high or inverted, with either of two pulsewidths and timings. sports support serial data word lengths from 3 bits to 16 bits and provide optional a-law and -law companding. ? sport receive and transmit sections can generate unique interrupts on completing a data word transfer. ? sports can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. an inter- rupt is generated after a data buffer transfer. ? sport0 has a multichannel interface to selectively receive and transmit a 24-word or 32-word, time-division multi- plexed, serial bitstream. ? sport1 can be configured to have two external interrupts ( irq0 and irq1 ), and the flag in and flag out signals. the internally generated serial clock may still be used in this configuration. the following are additional capabilities of the admc401 sports that are not part of the adsp-21xx products: ? sport1 is the input for single pin program and data memory boot loading. the rfs1 pin can be configured internally to the admc401 as an srom/e 2 prom reset signal. ? sport1 has two data receive pins (dr1a and dr1b). the dr1a pin is intended only for synchronous data receive from the external e 2 prom. the dr1b pin can be used as the data receive pin for a general purpose sport after boot- ing or as the data receive pin for other boot load modes or as the uart/debugger interface. the dr1a and dr1b pins are internally multiplexed onto the one data receive pin of the sport. the particular data receive pin selected is deter- mined by bit 4 of the modectrl register.
admc401 C17C rev. b pin function description the admc401 is available in an 144-lead tqfp package. table i contains the pin descriptions. table i. pin list pin # group of input/ name pins output function a13Ca0 14 o address lines d23Cd0 24 i/o data lines pms , dms , bms 3 o external memory select lines rd , wr 2 o external memory read/write enable mmap 1 i memory map select por 1 o internal power on reset output reset 1 i processor reset input clkout 1 o processor clock output clkin, xtal 2 i, o external clock or quartz crystal input br 1 i bus request bg , bgh 2 o bus grant and bus hang control bmode 1 i boot mode select pwd , pwdack 2 i, o power-down and power-down acknowledge sport0 5 i/o serial port 0 pins (tfs0, rfs0, dt0, dr0, sclk0) sport1 6 i/o serial port 1 (tfs1/ irq1 , rfs1/ irq0 / srom , dt1/fo, dr1a/fi, dr1b/fi, sclk1) vin0Cvin7 8 i analog inputs ashan, bshan 2 i inverting inputs to sample and hold amplifiers gain 1 i analog input for gain calibration v ref 1 i/o reference voltage input/output refcom 1 gnd reference common cml 1 o common- mode level (midsupply) capt, capb 2 o noise reduction pins sense 1 i voltage reference select convst 1 i external convert start ah-cl 6 o pwm outputs pwmtrip 1 i pwm shutdown signal pwmpol 1 i pwm polarity control pwmsync 1 o pwm synchronization output pwmsr 1 i pwm switched reluctance mode control pio0Cpio11 12 i/o digital i/o port etu0, etu1 2 i event timer inputs aux0Caux1 2 o auxiliary pwm outputs eia, eib, eiz, eis 4 i encoder interface inputs and external registration inputs nc 2 no connect avdd 2 sup analog power supply avss 2 gnd analog ground vdd 8 sup digital power supply gnd 16 gnd digital ground interrupt overview the admc401 can respond to different interrupt sources, some of which are internal dsp core interrupts and others from the motor control peripherals. the dsp core interrupts include a: ? power up (or reset ) interrupt. ? a peripheral (or irq2) interrupt. ? a sport0 receive and a sport0 transmit interrupt. ? a sport1 receive (or irq0 ) and a sport1 transmit (or irq1 ) interrupt. ? two software interrupts. ? an interval timer timeout interrupt. ? a power-down interrupt. in addition, the motor control peripherals add other interrupts that include: ? a pwmsync interrupt. ? an adc end of conversion interrupt. ? an encoder loop timer timeout interrupt. ? five peripheral input/output (pio) interrupts. ? an event timer interrupt. ? an encoder count error interrupt. ? a pwm trip interrupt. the interrupts are internally prioritized and individually maskable except for the nonmaskable power-down interrupt. memory map the admc401 has two distinct memory types; program memory and data memory (in addition to external boot memory). in general, program memory contains user code and coefficients, while the data memory is used to store variables and data during program execution. both program memory ram and rom is provided internally on the admc401. the program memory map of the admc401 can be altered depending on the state of the mmap and bmode pins. the various program memory maps are illustrated in figure 11 for the permissible settings of mmap and bmode. the state of these pins also impact the way in which the internal memory of the admc401 is b ooted, as described later. there is 2k of internal rom on the admc401. setting the romenable bit on the data memory wait state control register (at address dm (0x3ffe)) enables the rom. when the romenable bit is set to 1, addressing program memory in the rom range will access the on-chip rom. when romenable is set to zero, addressing program memory in this range will access external program memory. the romenable bit is initialized to zero after reset unless mmap and bmode = 1. when mmap = bmode = 0, the admc401 provides 2k 24 bits of internal program memory ram starting at address 0x0000 that is booted from a byte-wide interface on the address and data buses. following boot loading, program execution starts at address 0x0000. in this mode, the remainder of the program memory space, a 12k 24-bit block starting at address 0x1000, is assigned to external memory. when mmap = bmode = 1, the program memory map is identical to the previous case, but romenable defaults to 1 at reset, and execution starts from the internal program memory rom located at address 0x0800. this permits the internal (and external if desired) memory to be boot loaded across the various serial interfaces on sport1.
rev. b admc401 C18C when mmap = 1 and bmode = 0, the internal program memory ram is mapped to the top of the program memory space (starting at address 0x3800) and no boot loading occurs. program execution starts from external program memory at address 0x0000. only with romenable = 1 are the internal rom monitor and debugger features of the admc401 available for program development. additionally, certain spaces of the memory map have predefined functions as illustrated in figure 12 where it can be seen that address space 0x0000 to 0x005f is reserved for the interrupt vector table. vector table user program space 0x000 rom monitor reserved external memory 0x05f 0x060 0x7ff 0x800 0xfef 0xff0 0xfff 0x1000 figure 12. detailed view of program memory map with mmap = bmode = 1 the program memory interface can generate 0 to 7 wait states for external memory devices. the program memory wait state field (pwait) in the system control register controls the number of inserted wait states and defaults to 7. the structure of the system control register is shown at the end of the data sheet. the data memory map of the admc401 is shown in figure 13. the internal data memory ram of the admc401 is arranged as a single 1k 16-bit block starting at address 0x3800. in addition, there are two 1k blocks of reserved data memory space; one block starting at address 0x2000 that is reserved for the peripheral registers and one starting at address 0x3c00 that is reserved for internal dsp core registers. data memory wait states are controlled by the dwait0, dwait1, dwait2, dwait3 and dwait4 fields of the data memory wait state register (memwait) as illustrated in figure 13. following reset, dwait0 = dwait1 = dwait2 = dwait 3 = dwait4 = 7. however, in standalone mode with mmap = bmode = 1, the internal monitor code writes 0 to these five fields. for correct operation dwait2 must always be 0. the configuration of the memwait register is shown at the end of the data sheet. 0x0000 8k external memory 0x23ff 0x2400 0x1fff 0x2000 peripheral registers 5k external memory dsp core registers/ reserved internal user ram 0x37ff 0x3800 0x3bff 0x3c00 0x3fff 0x3b5f 0x3b60 reserved by monitor 0x0000 0x03ff 0x0400 dwait0 0x2fff 0x3000 0x3fff dwait1 dwait2 no wait states 0x07ff 0x0800 dwait3 dwait4 0x3400 0x3800 figure 13. data memory map of the admc401 rom code the 2k 24-bit block of internal program memory rom start- ing at address 0x800 contains a monitor function that can be used to download and execute user programs via the serial port. in addition, the monitor function supports an interactive mode in which commands are received and processed from a host that is configured as a uart device. an example of such a host is the windows-based motion control debugger that is part of the software development system for the admc401. in the interactive mode, the host can access both the internal dsp and peripheral motor control registers of the admc401, read and write to both program and data memory, implement break- points and perform single-step operation as part of the program debugging cycle. again, this debugging feature is only available when romenable = 1. 2k internal ram (booted from byte-wide eprom) 2k internal rom (romenable = 1) or 2k external (romenable = 0) 12k external memory 0x0000 0x0fff 0x1000 0x07ff 0x0800 0x3fff mmap = 0 bm o de = 0 2k external memory 10k external memory 0x0000 0x0fff 0x1000 0x07ff 0x0800 0x3fff mmap = 1 bm o de = 0 2k internal ram (booted via sport1) 2k internal rom (romenable defaults to 1 during reset) 0x0000 0x0fff 0x1000 0x07ff 0x0800 0x3fff mmap = 1 bmode = 1 0x3800 2k internal ram 2k internal rom (romenable = 1) or 2k external (romenable = 0) 12k external memory figure 11. program memory map of admc401
admc401 C19C rev. b system interface clock signals the admc401 uses an input clock with a frequency equal to half the instruction rate; a 13 mhz input clock yields a 38.5 ns processor cycle (which is equivalent to 26 mhz). normally instructions are executed in a single processor cycle. all device timing is relative to the internal instruction rate, which is indi- cated by the clkout signal (when enabled). throughout this data sheet, the period of the clkin signal is denoted by t cki . the dsp instruction period is t ck (the period of the clkout signal), and t ck = 0.5 t cki . for 26 mips operation, a 13 mhz clkin signal is used, corresponding to t cki = 76.9 ns and t ck = 38.5 ns. additionally, t ck is the fundamental time increment of the motor control peripherals. therefore, unless otherwise specified, the motor control peripherals are clocked at a rate equal to clkout. the admc401 can be clocked by either a crystal or by an external clock source. the clkin input cannot be halted, changed in frequency, or operated below the specified minimum frequency during normal operation. if an external clock source is used, it should be a ttl-compat ible signal running at half the instruction rate. the signal is con- nected to the clkin pin of the admc401. in this mode, with an external clock signal, the xtal pin must be left unconnected. because the admc401 includes an on-chip oscillator circuit, an external crystal may be used instead of a clock source. the crystal should be connected across the clkin and xtal pins. a parallel-resonant, fundamental frequency, microprocessor- grade crystal should be used. the frequency value selected for the crystal should be equal to half the desired instruction rate for the processor. figure 15 shows a 13 mhz crystal properly connected to yield a 26 mhz processor rate. the clkout output can be enabled and disabled by the clkodis bit of the sport0 autobuffer control register, dm (0x3ff3). however, extreme care must be exercised when using this bit (and is thus discouraged) since disabling clkout effectively disables all motor control peripherals, except the watchdog timer. reset and power-on reset circuit the reset pin initiates a complete hardware reset of the admc401 when pulled low. the reset signal must be asserted when the device is powered up to assure proper initialization. the admc401 contains an integrated power-on reset c ircuit that provides an output reset signal, por , from the admc401 on power up and if the power supply voltage falls below the threshold level. the admc401 may be reset from an external source using the reset signal or alternatively the internal power-on reset circuit may be used by connecting the por pin to the reset pin. during power-up the reset line must be activated for long enough to allow the dsp cores internal clock to stabilize. the power-up sequence is defined as the total time required for the crystal oscillator to stabilize after a valid v dd is applied to the processor and for the internal phase locked loop (pll) to lock onto the specific crystal frequency. a m inimum of 2000t cki cycles will ensure that the pll has locked (this does not include the crystal oscillator start-up time). the operation of the internal power-on reset circuit is illustrated in figure 14. on power-up, the circuit maintains the por pin low until it detects that the v dd line has attained the threshold voltage, v rst level. as soon as the threshold voltage is attained, the power on reset circuit enables a 17-bit counter that is clocked at the clkout rate. while the counter is counting the por pin is held low. when the counter overflows, after a time: tms rst = = 2 38 5 10 2 52 16 9 .. C the por pin is brought high and if the por and reset pins are connected, the device is brought out of reset. the internal power-on reset circuit also acts as a power supply monitor and puts the por pin at a lo level if it detects a volt- age less than v rst Cv hyst , where v hyst is the hysteresis voltage built into the por circuit. the supply voltage must then exceed v rst to initiate another power-on reset sequence. vdd por t rst t rst v rst v rst - v hyst figure 14. operation of power-on reset (por) circuit of admc401 the master reset ( reset = lo) causes a full system reset, which sets all internal stack pointers to the empty stack condi- tion, masks all interrupts, clears the mstat register, restores the program counter to its initial value and performs a full reset of all of the motor control peripherals including the watchdog timer. following a power-up, it is possible to initiate a full system reset by simply pulling the reset low. for these resets, there is no need to wait for pll stabiliza tion and the reset signal must meet the minimum pulsewidth specifica- tion, t rsp . to generate the external reset signal, it is recom- mended to use either an rc circuit with a schmitt trigger or a commercially available reset ic. separate from a full system reset, a softw are co ntrolled periph- eral reset (exclu ding the watchdog tim er) is achieved by toggling the dsp fl2 flag with the following code segment: preset: set fl2; toggle fl2; toggle fl2; rts; a full dsp and peripheral reset (except the watchdog timer itself) will occur automatically on a watchdog trip. external memory interface the admc401 can address 14k 24 bits of external program memory and up to 13k 16 bits of external data memory. the admc401 provides the address on a 14-bit address bus (a13Ca0). instructions or data are transferred across the 24-bit data bus (d23Cd0) during program memory accesses. during data memory accesses, data is transferred on the 16 most signifi- cant bits (d23Cd8) of the data bus. for a dual off-chip fetch, the data from program memory is read first, then the data from data memory. the program memory select pin, pms , is acti- vated during external program memory accesses and can be used as a chip select signal for the external program memory devices. similarly, for external data memory accesses, the dms pin is activated.
rev. b admc401 C20C two control lines indicate the direction of the transfer. memory read, rd , is active low, signaling a read from external memory and memory write; wr , is active low, signaling a write to exter- nal memory. typically, the pms line is connected to the ce (chip enable) of the external program memory and the rd line is connected to the ce line of the external data memory. the rd line is connected to the oe (output enable) and the wr line is connected to the we (write enable) of both memories. on-chip accesses (to internal program memory ram and rom) do not drive any of the external signals. the pms , rd and the wr lines remain high (deasserted) and the address and data buses are three-stated during these internal accesses. similarly, internal accesses to data memory (including internal dm ram and peripheral and dsp core memory mapped registers) do not drive external signals and the dms , rd and the wr lines re- main high (deasserted) and the address and data buses are also three-stated. external peripherals can also be connected externally and memory mapped to the external memory space of the admc401. the 16 msbs of the external data bus are connected internally to the 16 bits of the internal data memory bus. therefore, the data lines d23Cd8 should be used for 16-bit peripherals. boot loading standalone mode (mmap = bmode = 1) boot loading of the admc401 may occur in a number of differ- ent ways and is determined by the state of both the mmap and bmode pins. if both mmap and bmode are tied to v dd (hi), the admc401 is placed in the so-called standalone mode and execution starts from internal program memory rom at address 0x0800 following a power-on or reset. this starts execu- tion of the internal monitor function that first performs some initialization functions (including writing 0 to the three data memory wait state fields) and copies a default interrupt vector table to addresses 0x0000C0x005f of program memory ram. the monitor program next clears bit 4 of the modectrl register to connect the dr1a pin to the internal data receive port (dr1) of sport1. in addition, bit 5 of the modectrl register is set. this connects the fl1 port of the dsp core to the rfs1/srom pin to act as a reset for a serial memory device. the monitor next attempts to boot load from an external serial rom (srom) or serial e 2 prom on sport1 using the three wire connection of figure 15. this srom or e 2 prom should be programmed with the protocol of the makeprom utility provided with the motion control debugger. the monitor program first toggles the rfs1/ srom pin of the admc401 to reset the serial memory device with the following code segment: sromreset: set fl1; toggle fl1; toggle fl1; rts; if a properly programmed srom or e 2 prom is connected to sport1, data is clocked synchronously into the admc401 at a rate of 1 mb/s. both internal and external program and data memory ram can be loaded from the srom/e 2 prom, up to the available capacity of the serial memory device. after the entire boot load is complete, program execution begins at ad- dress 0x0060. this is where the first instruction of the user code should be placed. v dd clkout mmap bmode reset xtal clkin dr1a sclk1 rfs1/ srom serial rom or e 2 prom admc401 13mhz 20pf 20pf data clk reset figure 15. basic system configuration in standalone mode if boot loading from an srom or e 2 prom is unsuccessful, the monitor code reconfigures sport1 as a uart (setting both bit 4 and bit 5 of the modectrl register) and attempts to receive commands from an external device on this serial port using the dr1b pin. the monitor now waits for two bytes of information. these bytes are received asynchronously so that no clock is needed. the first byte is the autobaud byte and it is used to calculate the baud rate at which data is being received. this is known as the autobaud feature. the admc401 will automatically lock onto the baud rate of the external device if it is sent a byte of 0x70. the maximum baud rate that the admc401 will lock onto is 300 kb/s for a 26 mhz clkout. the second byte of information received is the header byte that uniquely identifies to the monitor which type of interface it is connected to. there are six different interfaces supported on the admc401. these includes: ? a uart boot loader such as from a motorola 68hc11 communicating over its serial communications interface (sci) port. ? a synchronous slave boot loader (the clock is external). ? a synchronous master boot loader (the admc401 provides the clock). ? a uart debugger interface such as the motion control debugger from analog devices. the monitor then processes commands received from the debugger over the uart interface. ? a synchronous master debugger interface. ? a synchronous slave debugger interface. detailed information on these software interfaces can be found in the uart boot loader protocol and uart debugger protocol appendices of the admc401 developers reference manual . byte-wide eprom boot mode (mmap = bmode = 0) if both the mmap and bmode pins are tied to gnd, the admc401 operates in the so-called eprom boot mode. in this mode the entire internal program memory, or any portion of it, can be loaded from an external source using a boot sequence over the memory interface. to allow boot loading from inexpen- sive 8-bit wide eprom devices, the processor loads data one byte at a time. the boot sequence can also be initiated after reset by software. boot memory is organized into eight pages, each of which is 8k bytes long. every fourth byte of a page is an empty byte except for the first one, which contains the page length. each set of three bytes between successive empty bytes contains one 24-bit instruction to be loaded into the internal pm ram of the dsp.
admc401 C21C rev. b the page length is read first and then bytes are loaded from the top of the page downwards. this causes shorter booting times for shorter pages. the length of the boot page is given as: page length = ( number of 24 -bit pm words/ 8) C 1 that is, a page length of 0 causes the boot address generator to generate byte addresses for eight words that reside in 32 sequen- tial eprom locations. a prom splitter utility (spl21), part of the motion control debugger tool set, calculates the proper page length for your program and orders the bytes of your program according to the proper protocol. more detailed information about the use of this prom splitter utility can be found in the booting from external eprom with mmap = bmode = 0 chapter of the admc401s developers reference manual . following a reset, if both mmap and bmode are lo, the boot sequence always boot loads page 0. after reset, boot load- ing can occur under program control from any one of up to eight different boot pages. the boot page select field (bpage) in the memory mapped system control register specifies which boot page is to be loaded. to boot from a specific boot page, first set the bpage bits to the desired value and set the boot force bit (bforce) of the system control register to initiate a boot sequence. the admc401 can boot its internal program memory from a single byte-wide cmos eprom such as the 27c64 or the 27c512. a low cost commodity-grade eprom with an indus- try-standard access time can be used. the number of wait states for the boot memory access is selected in the bwait field of the system control register. this field can be set to any value from 0 to 7 to set the number of wait states. the default value for the bwait field is 7 so that seven wait states are inserted into the reset-initiated boot loading sequence. timing of the boot memory access is identical to that of external program memory or external data memory accesses, except that the active strobe is bms rather than pms or dms . to address eight pages of 8k bytes each, 16 address lines are needed. the least significant 14 bits are output on the 14-bit address bus (a13 to a0) while the most significant two bits are output on the 2 msbs of the data bus (d23 and d22) during boot memory accesses. the data is read from the middle eight bits of the data bus (d15 to d8). the development tools for the admc401 support the creation of eprom target files capable of boot loading both internal and external program and data memory. external memory mode (bmode = 0, mmap = 1) in this mode, with bmode tied to gnd and mmap tied to v dd , the admc401 is placed in external memory mode and there is no boot loading. the effect of this mode is that the internal 2k bank of program memory ram is relocated from the bottom of memory (starting at address 0x0000) to the top of the program memory space (at address 0x3800). in this mode, program execution starts at external memory address 0x0000, at which point the first instruction must be placed. the mode in which bmode = 1 and mmap = 0 is not allowed on the admc401 and is an illegal state. the operation of the admc401 is neither guaranteed nor defined with bmode = 1 and mmap = 0. bus request/grant the admc401 can relinquish control of the external data and address buses to an external device. the external device requests the bus by asserting (low) the bus request signal br . br is an asynchronous input and if the admc401 is not performing an external access, it responds to the active br input in the follow- ing processor cycle by: ? three-stating the data and address buses and the pms , dms , bms , rd and wr output drivers. ? asserting the bus grant (bg) signal, and ? halting program execution (unless go mode is enabled). if go mode is enabled, (using the ena g-mode instruction) the admc401 continues to execute instructions from its inter- nal memory. it will not halt program execution until it encoun- ters an instruction that requires an external access, which includes an access to any motor control peripheral register. if go mode is not enabled, the admc401 always halts before granting the bus. the processors internal state is not affected by granting the bus, and the serial ports remain active during a bus grant, whether or not the processor core halts. if the admc401 is performing an external access when the br signal is asserted, it will not grant the buses until the cycle after the access completes. the entire instruction does not need to be completed when the bus is granted. if a single instruction re- quires two external accesses, the bus will be granted between the two accesses. the second access is performed after br is re- moved. when the br input is released, the admc401 releases the bg signal, re-enables the output drivers and continues pro- gram execution from the point where it stopped. bg is always deasserted in the same cycle that the removal of br is recognized. the bus request feature operates at all times, including when the admc401 is booting and when reset is active. during reset , bg is asserted in the same cycle that br is recognized. during booting, the bus is granted after the completion of load- ing of the current byte (including any wait states). using the bus request during booting is one way to bring the booting operation under control of a host computer. the admc401 has an additional output, bus grant hang, bgh , which lets it operate in a multiprocessor system with a minimum number of wasted cycles. the bgh pin asserts when the admc401 is ready to execute an instruction but is stopped because the external bus is granted to another device. the other device can release the bus by deasserting bus request. once the bus is released, the admc401 deasserts bg and bgh and executes the external access. power-down modes the admc401 includes a power-down feature that allows the device to enter a very low power dormant state through hard- ware or software control. in the power-down mode: ? internal clocks are disabled ? processor registers and memory contents are maintained ? ability to recover from power-down in less than 100t cki cycles ? interrupt support for housekeeping code before entering power-down and after recovering from power-down ? user-selectable power-up context
rev. b admc401 C22C entering power-down the power-down sequence is initiated by applying a high-to-low transition on the pwd pin or by setting the power-down force control bit (pdforce) of the sport1 autobuffer/power- down control register. the dsp core then vectors to the non- maskable power-down interrupt vector at address 0x002c. care must be taken to ensure that multiple power-down interrupts do not occur or else stack overflow may result. the interrupt ser- vice routine at address 0x002c can be used to execute any num- ber of housekeeping instructions prior to the processor entering the power-down mode. typically, this is used to configure the power-down state, disable on-chip peripherals and clear pending interrupts. the dsp subsequently enters the power-down mode when it executes the idle instruction (while pwd is asserted). the processor may take either one or two cycles to power down, depending on internal clock states during execution of the idle instruction. all register and memory contents are maintained in power-down. also, all active outputs are held in whatever state they are in before going into power-down. if an rti instruction is executed before the idle instruction, the processor returns from the power-down interrupt and the power-down sequence is aborted. exiting power-down the power-down mode can be exited with the use of the pwd pin or with the reset pin. there are also several user-select- able modes for startup from power-down which specify a start- up delay as well as specify the program flow after startup. this allows the program to resume from where it left off before power-down, or for the program context to be cleared. applying a low-to-high transition on the pwd pin will take the processor out of power-down. the amount of time it takes for the proces- sor to come out of power-down is controllable with the delay startup from power-down control bit (xtaldelay, bit 14 of the power-down control register or sport1 autobuffer control register). if this bit is cleared, no additional delay over the quick startup (100 cycles) is introduced. if this bit is set, a delay of 4096 cycles is introduced. the context for exiting power-down is set by bit 12 (pucr) of the power-down control register. if this bit is cleared, after exiting power-down the processor will continue to execute in- structions following the idle instruction after the low-to-high transition on the pwd pin. when the rti instruction is en- countered in the interrupt service routine for the power-down, operation is returned to the main routine. if the pucr bit is set, for a clear context, the processor resumes operation from power-down by clearing the pc, status, loop and cntr registers. the imask and astat registers are cleared and the sstat goes to 0x55. the processor starts execution at address 0x0000. active output pins retain their states during power-down. in addition, interrupts are latched and can be serviced if the admc401 exits power-down with pucr = 0. it is possible to clock data into or out of the serial ports during power-down by supplying an external serial clock. data clocked into the admc401 will remain in the rx registers. these activities cause additional power consumption. if reset is activated while the admc401 is in the power- down mode, power down is exited, and a normal full system reset sequence is initiated, (which depends upon the settings of mmap and bmode for the boot method as usual). when exiting power-down with reset , the xtaldelay control bit is ignored. startup time after power-down the time required to exit the power-down state depends on the method used to exit power-down. unlike the standard adsp- 21xx products, the xtaldis bit of the power-down register has no effect on the admc401 so that it is not possible to avoid the power drain caused by the xtal pin toggling. when the processor comes out of power-down by either the pwd or reset pins, it will begin executing after a maximum startup time of 100 clkin cycles as long as the clock oscillator is stable and at the same frequency as before power-down. if the external clock is unstable when the admc401 exits power-down, the xtaldelay control bit can be used to insert an additional 4096 cycle delay into the startup time. this delay can only be inserted when the admc401 is brought out of power-down by the pwd pin. if the processor is taken out of power-down by the reset line, and the clock is stable and at the same frequency as before power-down, the reset need only be held for five cycles. the pwdack pin the pwdack pin is an output that indicates when the admc401 is in the power-down mode. this pin is driven high by the pro- cessor when it has powered down. it is driven low after the processor has completed the power-up sequence. a low level on the pwdack pin also indicates that there is a valid clkout signal and that instruction execution has begun. when power-down is terminated with the reset pin or a start- up delay is selected, a low level on the pwdack pin only indi- cates the start of oscillations on the clkout pin. it will not necessarily indicate the start of instruction execution. the state of pwdack and also the clkout signal is unde- fined during the first 100 cycles of the initial reset. using power-down as a nonmaskable interrupt the power-down interrupt is never masked. it is possible to use this interrupt for other purposes, if desired. the admc401 does not go into power-down until the idle instruction is executed. if an rti is executed instead, before an idle instruction, the processor returns from the power-down interrupt service outline and the power-down sequence is aborted. the analog-to-digital conversion system overview of adc system the admc401 contains a fast, high accuracy, multiple-input analog-to-digital conversion system with simultaneous sampling capabilities. this a/d conversion system permits the fast, accu- rate conversion of currents, voltages and other signals needed in high performance motor control systems. a functional block diagram of the entire adc system is shown in figure 16. the adc system permits up to eight dedicated analog inputs all to be converted in under 2 s (at 26 mhz) through a single 12- bit pipeline flash adc. the entire adc system (including multiplexing and the sample and hold amplifiers) operates at a clock rate equal to a quarter of the dsp instruction rate. analog input voltages of up to 4.0 v p-p can be converted. the input signals are divided into two banks of four signals each, with vin0 to vin3 making up one bank and vin4 to vin7 making up the second bank. there are also two dedicated inputs ( ashan
admc401 C23C rev. b and bshan) to the inverting terminal of the two sample and hold amplifiers (sha) so that external signals can be correctly biased about the nominal operating range of the adc. adc0(15...0) adc1(15...0) adc2(15...0) adc3(15...0) adc4(15...0) adc5(15...0) adc6(15...0) adc7(15...0) adcotr(7...0) adcstat(4...0) adcctrl(4...0) multiplexer, sha and adc control internal reference signals ashan vin0 vin1 vin2 vin3 vin4 vin5 vin7 bshan pwmsync convst clkout capt capb v ref refcom sense cml vin6 voltage reference generation & control 12-bit pipeline flash adc data control signals end of conversion out of range mux mux mux sha a adcxtra(15...0) gain sha b pwmsync (from pwm peripheral) figure 16. functional block diagram of the adc system of the admc401 the basic architecture of the adc system consists of a four- stage pipeline architecture (the a/d core) with wideband input sample and hold amplifiers. excluding the last stage, each stage of the pipeline consists of a low resolution flash a/d connected to a switched capacitor dac and interstage residue amplifier (mdac). the reside amplifier amplifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. the last stage of the pipeline simply con- sists of a flash a/d. the pipeline architecture allows a greater throughput rate at the expense of pipeline delay or latency. this means that while the converter is capable of capturing a new input sample every adc clock cycle, it actually takes 3 1/2 adc clock cycles for the conversion process of any input to be fully processed and appear at the output. the adc may operate in two basic conversion modes, simulta- neous sampling or sequential sampling . the operating mode is selected by dedicated bits in the adcctrl register. in the simultaneous sampling mode, two analog inputs (one from each bank) are sampled simultaneously so that vin0 and vin4, vin1 and vin5, vin2 and vin6, vin3 and vin7 represent four pairs of simultaneously sampled inputs. in the alternative sequential operating mode, there is no simultaneous sampling, and the analog inputs are sampled and converted one after the other (i.e., vin0 followed by vin1 followed by vin2, etc.). in this mode, successive analog inputs are sampled an adc clock period (or four dsp clock cycles) apart. the conversion sequence may be initiated either internally (syn- chronized to the pwm generation) or from an external event on the convst pin. in the default simultaneous sampling mode of operation, the internal control logic simultaneously samples the first pair of input signals (vin0 and vin4) following the con- vert start command. subsequently, these inputs are multiplexed into the 12-bit analog-to-digital converter. after a delay of two adc clock cycles, the second pair of analog inputs (vin1 and vin5) are sampled simultaneously and then multiplexed into the adc. this process continues until all four pairs of analog inputs have been sampled and converted. as the conversion for a given analog input channel is completed, the corresponding digital number is written to a dedicated 16-bit, twos comple- ment, left-aligned register that is memory mapped to the data memory space of the dsp core. the adc data register adc0 stores the conversion result for the signal on vin0, etc. following the end of conversion of each pair of analog inputs, a dedicated bit is set in the adcstat register. the result of this highly efficient pipelined structure is that all eight adc data registers will contain valid conversion results less than 2 s (at 26 mhz) after the convert start command. at this point a dedi- cated adc interrupt will be generated. alternatively, if data is required sooner, the adcstat register can be polled to detect when a given pair of analog inputs have been successfully con- verted, except in sequential sampling mode. once the conversion sequence has been completed and all eight adc data registers have been updated, the entire adc structure automatically reverts to the single channel mode and continu- ously converts the analog input on the vin0 pin. the results of this conversion are placed in the additional adcxtra register and are updated once every adc clock cycle. this feature could be used to continuously monitor a single analog input on the vin0 pin. there are two additional modes of operation of the adc system that may be used for offset and gain calibration of the entire system. in the offset calibration mode, all analog inputs (vin0 to vin7, gain, ashan and bshan) are disconnected from the inputs to the sample and hold amplifiers. instead, both terminals of each sample and hold amplifiers are connected together and to the voltage reference. following a conversion sequence, the data in the adc data register can be taken as a measure of any offset in the sample and hold amplifiers and adc. additionally, in the gain calibration mode, the dedicated analog input gain is applied to the noninverting terminal of both sample and hold amplifiers. any number of precise exter- nal voltages can be applied to this pin to measure and correct for any gain errors, if required. along with each data output from the a/d converter, an out-of- range (otr) bit is set if the signal exceeds the permissible input voltage span. in normal conversion, the eight otr bits for the eight analog inputs are stored in the adcotr register, with one bit for each analog input. the otr bit for the adcxtra register is stored in the adcstat register. the adc may use either an internally generated 2.0 v precision reference voltage or an externally supplied reference voltage level at the v ref pin. the operating mode is selected by the connection of the sense pin.
rev. b admc401 C24C convert start command the analog-to-digital conversion process of the admc401 may be started by either an internal or an external command. bit 0 of the adcctrl register determines whether internal or external convert start mode is enabled. if bit 0 of the adcctrl regis- ter is cleared, internal convert start mode is selected, and the adc conversion process is started on the rising edge of the pwmsync signal. this results in one conversion sequence per pwm switching period (at the start of each period) when the pwm generation unit operates in the single update mode. in the double update operating mode, there are two conversion se- quences per pwm switching period (one at the start and one in the middle of each period). in internal convert start mode, in order to ensure correct synchronization and jitter-free operation, it is essential that the value written to the pwmtm register be a multiple of four. in other words, the two lsbs of the value written to the pwmtm register must both be 0. if bit 0 of the adcctrl register is set, external convert start mode is selected. in this mode, the conversion process is started on the occurrence of a rising edge on the convst pin. addi- tionally, the start of conversion can be placed under software control by externally connecting one of the programmable input/ output (pio) lines to the convst pin and generating a rising edge by writing to the appropriate bit of the piodata register. by default, following reset, bit 0 of the adcctrl register is cleared so that internal convert start mode is selected. adc clock signals the adc consists of a pipeline flash architecture and is clocked at a quarter of the dsp instruction rate. all of the timing of the adc system (including control of the multiplexers and sample and hold amplifiers) is regulated by this clock signal and it de- termines the total conversion time for all of the channels as well as the delay between sampling of successive pairs of analog inputs. the adc clock rate is internally fixed and may not be changed. the period of the adc clock, t ckadc is related to the dsp clkout period by: tt ckadc ck = 4 a dsp rate of 26 mhz corresponds to a t ckadc of approxi- mately 154 ns. analog input configuration and overview figure 17 is a simplified model of the adc input structure for one channel (vin0) of the adc system of the admc401. this model applies to all eight input channels. the internal multi- plexers are used to switch the various analog inputs to the a/d converter. for analog inputs vin0 to vin3, there is a single common terminal (ashan) that is the inverting input to the internal differential sample and hold amplifier. for the input signals, vin4 to vin7, the equivalent input is bshan. the value v ref (internally generated voltage reference or externally applied voltage reference on the v ref pin) defines the maximum input voltage to the a/d core. the minimum input voltage to the a/d core is automatically defined as Cv ref . +v ref v ref 12 vin0 ashan v core a/d core figure 17. equivalent functional input circuit of adc system the dc voltage on the v ref pin sets the common-mode voltage of the a/d converter of the admc401. for example, when using the internal 2.0 v reference, the input level will also be centered about 2.0 v. the adc inputs of the admc401 can be configured for single ended operation, where the inverting terminals (ashan and bshan) are connected directly to the reference voltage level, and the analog inputs (vin0 to vin7) are driven by analog signals with a 4.0 v p-p range. the vin0 to vin7 inputs are unipolar so that when operating from the internal 2.0 v reference, these signals can range from 0 v to 4 v. the recommended single-ended input configuration for a single analog input channel of the admc401 is shown in fig- ure 18. the input to the a/d converter must be driven by an operational amplifier with sufficient drive strength so that the a/d performance is not degraded. sufficient drive strength is the ability to drive a load of 6 pf static and 4 pf switched from ground (capacitive) to settle within 1.0 mv within 70 ns. in figure 18, the operational amplifier is shown configured as a simple noninverting input buffer. of course, the operational amplifier stage could also be used to implement any necessary level shifting and/or filtering of the input signal. +v v vin0 ashan v ref sense admc401 r s r s 10 f 0.1 f 4v 0v figure 18. typical single-ended input configuration for admc401 from figure 17, it is clear that the input to the a/d core is simply given by: v vin ashan core = 0C which must satisfy the condition: C vv v ref core ref ? where v ref is the voltage at the v ref pin of the admc401 (either internally generated or externally supplied). there is an additional limit placed on the valid operating range for the vin0 and ashan inputs that is bounded by the power supply of the admc401: av v vin av v av v ashan av v ss dd ss dd C. . C. . 03 0 03 03 03 ? + ?+
admc401 C25C rev. b simultaneous sampling mode this operating mode is selected by clearing both bits 3 and 4 of the adcctrl register. in this mode, the eight analog inputs are sampled as four pairs of simultaneously sampled inputs with vin0 and vin4 being the first pair of sampled inputs, followed by vin1 and vin5, followed by vin2 and vin6, followed by vin3 and vin7. following the rising edge of the convert start command (either internally or externally derived), the internal control logic simultaneously samples the vin0 and vin4 analog inputs using the dual internal sample and hold amplifiers. the internal control logic subsequently multiplexes these two signals into the a/d core of the admc401. the conversion of each signal requires 3 1/2 adc clock cycles. following the hold operation, the vin0 input is applied to the first stage of the pipeline during the next adc clock cycle. for the next clock cycle, the vin0 signal is applied to the second stage of the pipeline and the vin4 input is applied to the first stage of this pipeline. in this clock cycle, the second pair of inputs is also simultaneously sampled. this process continues to feed signals into the a/d core until all eight channels have been converted. the timing of this conversion sequence is shown in figure 19. convert vin7 s&h vin3 & vin7 s&h vin1 & vin5 s&h vin2 & vin6 convert start adc clock s&h vin0 & vin4 convert vin0 convert vin4 convert vin1 convert vin5 convert vin2 convert vin6 convert vin3 t ckadc figure 19. adc timing for simultaneous sampling oper- ating mode in this operating mode, there is a unique status bit in the adcstat register that is set as soon as data is available for each pair of simultaneously sampled signals. bit 0 of the adcstat is set as soon as the data in both the adc0 and adc4 registers is valid, bit 1 is set as soon as the data in adc1 and adc5 is valid, bit 2 is set as soon as the data in adc2 and table ii. digital data format of adc vin0 (v) ashan (v) vcore (v) digital data (hex) digital data (binary) otr 2 v ref v ref +v ref 0x7ff0 0111 1111 1111 0000 1 2 v ref C 1 lsb v ref v ref C 1 lsb 0x7ff0 0111 1111 1111 0000 0 2 v ref C 2 lsb v ref v ref C 2 lsb 0x7fe0 0111 1111 1110 0000 0 v ref + 1 lsb v ref 0 + 1 lsb 0x0010 0000 0000 0001 0000 0 v ref v ref 0 0x0000 0000 0000 0000 0000 0 v ref C 1 lsb v ref 0 C 1 lsb 0xfff0 1111 1111 1111 0000 0 0 + 1 lsb v ref Cv ref + 1 lsb 0x8010 1000 0000 0001 0000 0 0v ref Cv ref 0x8000 1000 0000 0000 0000 0 < 0 v ref rev. b admc401 C26C adc6 is valid and bit 3 is set when the data in adc3 and adc7 is valid. at the start of the next conversion sequence, all bits of the adcstat register are cleared. additionally, at the end of the complete conversion sequence (when the data in the adc7 register is valid), a dedicated adc interrupt is generated. this interrupt can be masked and controlled by the pic block. depending on initial synchronization delays, the worst case total conversion time (defined as the duration from the rising edge of the convert start command to the generation of the adc inter- rupt) for all eight channels is: t conv = 49 t ck which corresponds to 1.88 s for a dsp instruction rate of 26 mhz. additionally, in this operating mode, the time delay between sampling of successive pairs of analog inputs is 8t ck or 308 ns (at 26 mhz). sequential sampling mode this operating mode is selected by setting bit 3 and clearing bit 4 of the adcctrl register. in this operating mode, simul- taneous sampling is abandoned and the a/d conversion se- quence samples each analog input sequentially. therefore, in the first adc clock period, vin0 is sampled and held by the first sam ple and hold amplifier. in the second clock period, the held sample of vin0 is applied to the first stage of the adc pipeline and the vin1 signal is sampled. this process continues until each of the analog inputs has been sequentially sampled and converted (i.e., vin0 followed by vin1 followed by vin2, etc.). in this operating mode, the total conversion time is the same as the simultaneous sampling mode. however, successive channels are sampled at 4t ck (or 154 ns at 26 mhz) intervals. in this mode, bits 0 to 3 of the adcstat register are all set together when all eight conversions are complete. the interrupt is generated, as before, when the data in the adc7 register is valid. offset calibration mode in order to maintain the high accuracy of the adc system of the admc401, it may be necessary to measure and compensate for any intrinsic offset and/or gain errors in the a/d conversion system. the offset calibration mode, which is selected by setting bit 4 and clearing bit 3 of the adcctrl register, is intended to be used for measuring any offsets in the sample and hold amplifiers. when this mode is selected, all analog inputs (vin0 to vin7, ashan and bshan) are disconnected from the inputs to the sample and hold amplifiers, and the sha inputs are internally connected together and to the reference voltage (at the v ref pin). since these connections are in effect only during the conversion sequence, a complete conversion se- quence must be i nitiated. following the end of conversion, the data in the adc0 to adc3 registers may be taken as four separate measurements of the offset of the first sample and hold amplifier. similarly, the data in the adc4 to adc7 registers may be taken as measurements of the offset associated with the second sample and hold amplifier. these data values could be averaged to obtain an offset value for each sample and hold amplifier that could be stored and used to compensate all future measurements. the end of conversion status bits are updated and the interrupt is generated in a manner identical to the si- multaneous sampling mode. gain calibration mode it may be desirable to measure and compensate for any gain errors associated with the a/d conversion process across the entire input voltage span of the a/d system. the gain calibra- tion mode, selected by setting both bits 3 and 4 of the adcctrl register, is designed to offer significant user flexibility in deter- mining the amount of gain compensation that may be required. in this mode the dedicated gain input pin is internally con- nected directly to the noninverting input of each sample and hold amplifier. the user may apply different precise analog voltages across the input voltage span to this pin to measure gain errors over the operating range. a complete conversion sequence for each different gain input must be initiated. following the end of conversion, the data in the adc0 to adc3 registers may be used to calculate four separate measurements of the gain error of the first sample and hold amplifier. similarly, the data in the adc4 to adc7 regis- ters may be used to calculate the gain associated with the second sample and hold amplifier. these data values could be averaged to obtain gain error values for each sample and hold amplifier that could be stored and used to compensate all future measure- ments. the end of conversion status bits are updated and the interrupt is generated in a manner identical to the simulta- neous sampling mode. adcxtra register following the end of conversion sequence in any of the four operating modes, the a/d system reverts to its single channel mode. in this configuration, the multiplexers are set such that the vin0 input is continuously sampled and converted. the results of these conversions are placed in the dedic ated adcxtra register that is updated with the results of a new conversion every adc clock period (or 154 ns at 26 mhz). this feature permits the continuous tracking of a single analog input, if re- quired. the otr bit for these conversions is placed in bit 4 of the adcstat register. no interrupt is generated following these conversions and no other status bits are generated. the adcxtra register is not updated during the conversion se- quence of any of the four operating modes. voltage reference operation the admc401 contains an onboard bandgap reference that can be used to provide a precise 2.0 v output for use by the a/d system and externally on the v ref pin for biasing and levelC shifting functions. additionally, the admc401 may be config- ured to operate with an external reference applied to the v ref pin. the sense pin is used to select between internal and external references. the actual reference voltages used by the internal adc circuitry of the admc401 appear on the capt and capb pins. for correct operation of the internal voltage reference generation circuitry, either with internal or external reference, it is neces- sary to add a capacitor network between these pins, as shown in figure 20. a 10 f tantalum capacitor in parallel with a 0.1 f ceramic is recommended as well as two 0.1 f capacitors to analog ground. the internal bias circuitry may take up to 15 ms after power-up to settle. any adc conversions performed prior to this may not be as accurate as possible. the start-up time may be evaluated by measuring how long it takes for the voltage difference between capt and capb to settle to v ref . addi- tionally, a 0.1 f ceramic capacitor must be connected between the cml pin and analog ground. finally, the v ref pin should be decoupled to analog ground by a 10 f tantalum capacitor in parallel with a 0.1 f ceramic capacitor.
admc401 C27C rev. b the sense pin controls whether the a/d system operates with an internal or an external reference. for operation with the internal refe rence, the sense pin should be tied to the refcom pin. in this mode, the internally derived 2 v voltage reference ap- pears at the v ref pin. to operate with an external voltage refer- ence, the sense pin should be tied to the av dd pin and the external voltage reference may be applied at the v ref pin. refcom sense 0.1 f cml capb admc401 capt v ref 0.1 f 0.1 f 10 f 0.1 f 0.1 f 10 f figure 20. recommended capacitor decoupling networks for the admc401 optimizing adc performance the optimum noise and dc linearity performance is achieved with the largest input signal voltage span (i.e., 4 v input span) and with matching impedance in series with each of the analog inputs (vin0 to vin7, ashan and bshan). additionally, the operational amplifier must exhibit source impedance that is both low and resistive, up to and beyond the sampling frequency. when a capacitive load is switched onto the output of the opera- tional amplifier, the output will momentarily drop, due to its effective output impedance. as the output recovers, ringing may occur. to remedy this situation, a series resistor can be inserted between the op amp output and the adc input (r s as shown in figure 18). recommended configurations include using the op27 amplifiers with an r s of 20 ? . alternative recommended op amps are the ad8051 and ad8054. figure 18 shows ashan driven by the internally generated reference voltage at v ref . when driving ashan with an inter- nally generated v ref , better performance will result if the driv- ing impedance of ashan matches the driving impedance of the other analog inputs. this can be implemented with the addition of a second amplifier to figure 18, between v ref and ashan, to match the amplifier on vin0. for noise sensitive applications, it may also be beneficial to add some shunt capacitance between the inputs (vin0 and ashan of figure 18) and analog ground. since this additional capaci- tance combines with the equivalent input capacitance of the analog inputs, a lower series resistance may be possible. the input rc combination also provides some antialiasing filtering on the analog inputs. to optimize performance when noise is the primary consideration, increase the shunt capacitance as much as the transient response of the input signal will allow. increasing the capacitance too much may adversely affect the op amps settling time, frequency response and distortion performance. adc registers the configuration and structure of the adc registers is de- scribed at the end of this data sheet. the pwm controller overview the pwm generator block of the admc401 is a flexible, pro- grammable, three-phase pwm waveform generator that can be programmed to generate the required switching patterns to drive a three-phase voltage source inverter for ac induction (acim) or permanent magnet synchronous (pmsm) motor control. in addition, the pwm block contains special functions that consid- erably simplify the generation of the required pwm switching patterns for control of the electronically commutated motor (ecm) or brushless dc motor (bdcm). a special mode for switched reluctance motors (srm) exists as well, enabled by a dedicated pin. the pwm generator produces three pairs of pwm signals on the six pwm output pins (ah, al, bh, bl, ch and cl). the six pwm output signals consist of three high side drive signals (ah, bh and ch) and three low side drive signals (al, bl and cl). the polarity of the generated pwm signals may be pro- grammed by the pwmpol pin, so that either active hi or active lo pwm patterns can be produced by the admc401. the switching frequency, dead time and minimum pulsewidths of the generated pwm patterns are programmable using respec- tively, the pwmtm, pwmdt and pwmpd registers. in addi- tion, three duty-cycle control registers (pwmcha, pwmchb and pwmchc) directly control the duty cycles of the three pairs of pwm signals. each of the six pwm output signals can be enabled or disabled by separate output enable bits of the pwmseg register. in addition, three control bits of the pwmseg register permit crossover of the two signals of a pwm pair for easy control of ecm or bdcm. in crossover mode, the pwm signal destined for the high side switch is diverted to the complementary low- side output and the signal destined for the low side switch is diverted to the corresponding high side output signal. in addi- tion to ease of use of the pwm controller for ecm or bdcm, this crossover mode can also be used to transition the pwm signals into the overmodulation range with relative ease. in many applications, there is a need to provide an isolation barrier in the gate-drive circuits that turn on the power devices of the inverter. in general, there are two common isolation tech- niques, optical isolation using opto-isolators and transformer isolation using pulse transformers. the pwm controller of the admc401 permits mixing of the output pwm signals with a high-frequency chopping signal to permit easy interface to such pulse transformers. the features of this gate-drive chopping mode can be controlled by the pwmgate register. there is an 8-bit value within the pwmgate register that directly controls the chopping frequency. in addition, high frequency chopping can be independently enabled for the high side and the low side outputs using separate control bits in the pwmgate register. also, all pwm outputs have sufficient sink and source capability to directly drive most opto-isolators. the pwm generator is capable of operating in two distinct modes, single update mode or double update mode. in single update mode the duty cycle values are programmable only once per pwm period, so that the resultant pwm patterns are sym- metrical about the midpoint of the pwm period. in the double update mode, a second updating of the pwm registers is imple- mented at the midpoint of the pwm period. in this mode, it is possible to produce asymmetrical pwm patterns that produce
rev. b admc401 C28C lower harmonic distortion in three-phase pwm inverters. this technique also permits closed loop controllers to change the average voltage applied to the machine windings at a faster rate and so permits faster closed loop bandwidths to be achieved. the operating mode of the pwm block (single or double update mode) is selected by a control bit in modectrl register. the pwm generator of the admc401 also provides an output pulse on the pwmsync pin, which is synchronized to the pwm switching frequency. in single update mode a pwmsync pulse is produced at the start of each pwm period. in double update mode, an additional pwmsync pulse is prod uced at the mid- point of each pwm period. the width of the pwmsync pulse is programmable through the pwmsyncwt register. the pwm signals produced by the admc401 can be shut off in a number of different ways. first, there is a dedicated asyn- chronous pwm shutdown pin, pwmtrip , that, when brought lo, instantaneously places all six pwm outputs in the off state (as determined by the state of the pwmpol pin). in addition, each of the pio lines of the admc401 (pio0 to pio11) can be configured to act as an additional pwm shut- down. by setting the appropriate bit in the piopwm register, the corresponding pio line acts as an asynchronous pwm shut- down source in a manner identical to the pwmtrip pin. these two hardware shutdown mechanisms are asynchronous so that the associated pwm disable circuitry does not go through any clocked logic, thereby ensuring correct pwm shutdown even in the event of a loss of the dsp clock. in addition to the hardware shutdown features, the pwm system may be shut down in soft- ware by writing to the pwmswt register. status information about the pwm system of the admc401 is available to the user in the sysstat register. in particular, the state of the pwmtrip and pwmpol pins is available, as well as status bits that indicates whether operation is in the first half or the second half of the pwm period. a functional block diagram of the pwm controller is shown in figure 21. the generation of the six output pwm signals on pins ah to cl is controlled by four important blocks: ? the three-phase pwm timing unit, which is the core of the pwm controller, generates three pairs of complemented and dead time adjusted center based pwm signals. ? the output control unit allows the redirection of the out- puts of the three-phase timing unit for each channel to either the high side or the low side output. in addition, the output control unit allows individual enabling/disabling of each of the six pwm output signals. ? the gate drive unit provides the correct polarity output pwm signals based on the state of the pwmpol pin. the gate drive unit also permits the generation of the high- frequency chopping frequency and its subsequent mixing with the pwm signals. ? the pwm shutdown controller takes care of the various pwm shutdown modes (via the pwmtrip pin, the pio lines or the pwmswt register) and generates the correct reset signal for the timing unit. the pwm controller is driven by a clock at the same frequency as the dsp instruction rate, t ck and is capable of generating two interrupts to the dsp core. one interrupt is generated on the occurrence of a rising edge of the pwmsync pulse and the other is generated on the occurrence of any pwm shutdown action. ah pwmcha (15 0) pwmchb (15 0) pwmchc (15 0) pwmseg (8 0) pwmgate (9 0) three-phase pwm timing unit output control unit clk sync reset sync gate drive unit clk pol clkout pwmtm (15 0) pwmdt (9 0) pwmpd(9 0) pwmsyncwt(7 0) modectrl (6) pwmswt (0) piopwm (11 0) al bh bl ch cl pwmtrip pwmsync pwmpol pio0 pio11 to interrupt controller pwm configuration registers pwm duty cycle registers pwmsync pwmtrip pwm shutdown controller sr pwmsr or pio pwm detect figure 21. overview of the admc401 pwm controller three-phase timing unit the 16-bit three-phase timing unit is the core of the pwm controller and produces three pairs of pulsewidth modulated signals with high resolution and minimal processor overhead. the outputs of this timing unit are active lo such that a low level is interpreted as a command to turn on the associated power device. there are four main configuration registers (pwmtm, pwmdt, pwmpd and pwmsyncwt) that determine the fundamental characteristics of the pwm outputs. in addition, the operating mode of the pwm (single or double update mode) is selected by bit 6 of the modectrl register. these registers, in conjunction with the three 16-bit duty cycle registers (pwmcha, pwmchb and pwmchc), control the output of the three-phase timing unit. pwm switching frequency, pwmtm register the pwm switching frequency is controlled by the 16-bit pwm period register, pwmtm. the fundamental timing unit of the pwm controller is t ck (dsp instruction rate). therefore, for a 26 mhz clkout, the fundamental time increment is 38.5 ns. the value written to the pwmtm register is effectively the number of t ck clock increments in half a pwm period. the required pwmtm value as a function of the desired pwm switching frequency (f pwm ) is given by: pwmtm f f f f clkout pwm clkin pwm = = 2 therefore, the pwm switching period, t s , can be written as: t pwmtm t sck = 2
admc401 C29C rev. b for example, for a 26 mhz clkout and a desired pwm switching frequency of 10 khz (t s = 100 s), the correct value to load into the pwmtm register is: pwmtm = = 26 10 21010 1300 6 3 the largest value that can be written to the 16-bit pwmtm register is 0xffff = 65,535, which corresponds to a minimum pwm switching frequency of: fhz pwm min , , = = 26 10 2 65 535 198 6 pwm switching dead time, pwmdt register the second important parameter that must be set up in the initial configuration of the pwm block is the switching dead time. this is a short delay time introduced between turning off one pwm signal (say ah) and turning on the complementary signal, al. this short time delay is introduced to permit the power switch being turned off (ah in this case) to completely recover its blocking capability before the complementary switch is turned on. this time delay prevents a potentially destructive short-circuit condition from developing across the dc link capacitor of a typical voltage source inverter. the dead time is controlled by the 10-bit pwmdt register. there is one dead time register that controls the dead time inserted into the three pairs of pwm output signals. the dead time, t d , is related to the value in the pwmdt register by: t pwmdt t dck = 2 therefore, for a 26 mhz clkout, a pwmdt value of 0x00a (= 10) introduces a 770 ns delay between the turn-off on any pwm signal (say ah) and the turn-on of its comple men- tary signal (al). the am ount of the dead time can therefore be progra mmed in increments of 2t ck (or 77 ns for a 26 mhz clkout). the pwmdt register is a 10-bit register so that its maximum value is 0x3ff (= 1023) corresponding to a maximum programmed dead time of: tt s d max ck , C .. === 1023 2 1023 2 38 5 10 78 8 9 for a clkout rate of 26 mhz. obviously, the dead time can be programmed to be zero by writing 0 to the pwmdt register. pwm o perating mode, modectrl and sysstat registers the pwm controller of the admc401 can operate in two distinct modes; single update mode and double update mode. the operating mode of the pwm controller is determined by the state of bit 6 of the modectrl register. if this bit is cleared, the pwm operates in the single update mode. setting bit 6 places the pwm in the double update mode. by default, following reset, bit 6 of the modectrl register is cleared so that the default operating mode is in single update mode. in single update mode, a single pwmsync pulse is produced in each pwm period. the rising edge of this signal marks the start of a new pwm cycle and is used to latch new values from the pwm configuration registers (pwmtm, pwmdt, pwmpd and pwmsyncwt) and the pwm duty cycle registers (pwmcha, pwmchb and pwmchc) into the three-phase timing unit. in addition, the pwmseg register is also latched into the output control unit on the rising edge of the pwmsync pulse. in effect, this means that the characteristics and resultant duty cycles of the pwm signals can be updated only once per pwm period at the start of each cycle. the result is that pwm patterns that are symmetrical about the midpoint of the switch- ing period are produced. in double update mode, an additional pwmsync pulse is produced at the midpoint of each pwm period. the rising edge of this new pwmsync pulse is again used to latch new values of the pwm configuration registers, duty cycle registers and the pwmseg register. as a result it is possible to alter the charac- teristics (switching frequency, dead time, minimum pulsewidth and pwmsync pulsewidth) as well as the output duty cycles at the midpoint of each pwm cycle. consequently, it is possible with double update mode to produce pwm switching patterns that are not symmetrical about the midpoint of the period (asym- metrical pwm patterns). in the double update mode, it may be necessary to know whether operation at any point in time is in either the first half or the second half of the pwm cycle. this information is provided by bit 3 of the sysstat register, which is cleared during opera- tion in the first half of each pwm period (between the rising edge of the original pwmsync pulse and the rising edge of the new pwmsync pulse introduced in double update mode). bit 3 of the sysstat register is set during operation in the second half of each pwm period. this status bit allows the user to make a determination of the particular half-cycle during implementation of the pwmsync interrupt service routine, if required. the advantage of the double update mode is that lower harmonic voltages can be produced by the pwm process and faster control bandwidths are possible. however, for a given pwm switching frequency, the pwmsync pulses occur at twice the rate in the double update mode. since new duty cycle values must be computed in each pwmsync interrupt service routine, there is a larger computational burden on the dsp in the double update mode. alternatively, the same pwm update rate may be maintained at half the switching frequency to give lower switch- ing losses. width of the pwmsync pulse, pwmsyncwt register the pwm controller of the admc401 produces an output pwm synchronization pulse at a rate equal to the pwm switch- ing frequency in single update mode and at twice the pwm frequency in the double update mode. this pulse is available for external use at the pwmsync pin. the width of this pwmsync pulse is programmable by the 8-bit read/write pwmsyncwt register. the width of the pwmsync pulse, t pwmsync , is given by: t t pwmsyncwt pwmsync ck = + () 1 so that the width of the pulse is programmable from t ck to 256 t ck (corresponding to 38.5 ns to 9.85 s for a clkout rate of 26 mhz). following a reset, the pwmsyncwt register con- tains 0x27 (= 39) so that the default pwmsync width is 1.54 s, again for a 26 mhz clkout. pwm duty cycles, pwmcha, pwmchb, pwmchc registers the duty cycles of the six pwm output signals on pins ah to cl are controlled by the three 16-bit read/write duty cycle registers, pwmcha, pwmchb and pwmchc. the integer value in the register pwmcha controls the duty cycle of the signals on ah and al, in pwmchb controls the duty cycle of the signals on bh and bl and in pwmchc controls the duty
rev. b admc401 C30C cycle of the signals on ch and cl. the duty cycle registers are programmed in integer counts of the fundamental time unit, t ck , and define the desired on-time of the high side pwm s ignal produced by the three-phase timing unit over half the pwm pe- riod. the switching signals produced by the three-phase timing unit are also adjusted to incorporate the programmed dead time value in the pwmdt register. the three-phase timing unit produces active lo signals so that a lo level corresponds to a command to turn on the associated power device. a typical pair of pwm outputs (in this case for ah and al) from the timing unit are shown in figure 22 for operation in single update mode. all illustrated time values indicate the integer value in the associated register and can be converted to time by simply multiplying by the fundamental time increment, t ck . first, it is noted that the switching patterns are sy mmetrical about the midpoint of the switching period in this single up- date mode since the same values of pwmcha, pwmtm and pwmdt are used to define the signals in both half cycles of the period. it can be seen how the programmed duty cycles are adjusted to incorporate the desired dead time into the resultant pair of pwm signals. clearly, the dead time is incorporated by moving the switching instants of both pwm signals (ah and al) away from the instant set by the pwmcha register. both switching edges are moved by an equal amount (pwmdt t ck ) to preserve the symmetrical output patterns. also shown is the pwmsync pulse whose width is set by the pwms yncwt register and bit 3 of the sysstat register, which indicates whether operation is in the first or second half cycle of the pwm period. pwmsync ah al pwmcha pwmcha 2 pwmdt pwmsyncwt + 1 2 pwmdt sysstat (3) pwmtm pwmtm figure 22. typical pwm outputs of three-phase timing unit in single update mode (active lo waveforms) the resultant on-times of the pwm signals over the full pwm period (two half periods) produced by the pwm timing unit, and illustrated in figure 22, may be written as: t pwmcha pwmdt t ah ck = () 2C t pwmtm pwmcha pwmdt t al ck = () 2CC and the corresponding duty cycles are: d t t pwmcha pwmdt pwmtm ah ah s == C d t t pwmtm pwmcha pwmdt pwmtm al al s == CC obviously negative values of t ah and t al are not permitted and the minimum permissible value is zero, corresponding to a 0% duty cycle. in a similar fashion, the maximum value is t s , corre- sponding to a 100% duty cycle. the output signals from the timing unit for operation in double update mode are shown in figure 23. this illustrates a com- pletely general case where the switching frequency, dead time and duty cycle are all changed in the second half of the pwm period. of course, the same value for any or all of these quanti- ties could be used in both halves of the pwm cycle. however, it can be seen that there is no guarantee that symmetrical pwm signals will be produced by the timing unit in this double update mode. additionally, it is seen that the dead time is inserted into the pwm signals in the same way as in the single update mode. pwmcha 2 2 pwmdt 1 2 pwmdt 2 pwmsyncwt 2 + 1 pwmcha 1 pwmtm 1 pwmtm 2 pwmsyncwt 1 + 1 ah al pwmsync sysstat (3) figure 23. typical pwm outputs of three-phase timing unit in double update mode (active lo waveforms) in general the on-times of the pwm signals over the full pwm period in double update mode can be defined as: t pwmcha pwmcha pwmdt pwmdt t ah ck =+ () 1212 CC t pwmtm pwmtm pwmcha pwmcha pwmdt pwmdt t al ck =+ ( ) 12 1 212 CC CC where the subscript 1 refers to the value of that register during the first half cycle and the subscript 2 refers to the value during the second half cycle. the corresponding duty cycles are: d t t pwmcha pwmcha pwmdt pwmdt pwmtm pwmtm ah ah s == + + 1212 12 CC d t t pwmtm pwmtm pwmcha pwmcha pwmdt pwmdt pwmtm pwmtm al al s == ++ + 121212 12 CCC since for the completely general case in double update mode, the switching period is given by: t pwmtm pwmtm t sck =+ () 12 again, the values of t ah and t al are constrained to lie between zero and t s. similar pwm signals to those illustrated in figure 22 and figure 23 can be produced on the bh, bl, ch and cl outputs by programming the pwmchb and pwmchc registers in a manner identical to that described for pwmcha. special consideration for pwm operation in overmodulation the pwm timing unit is capable of producing pwm signals with variable duty cycle values at the pwm out put pins. at the extremities of the modulation process, both 0% and 100% modulation are possible. these two modes are termed full off and full on respectively. in between, for other duty cycle val- ues, the operation is termed normal modulation .
admc401 C31C rev. b ? full on: the pwm for any pair of pwm signals is said to operate in full on when the desired hi side output of the three-phase timing unit is in the on state (lo) between successive pwmsync pulses. this state may be entered by virtue of the commanded duty cycle values (in conjunction with the pwmdt register) or by virtue of the correct opera- tion of the pulse deletion circuit. ? full off: the pwm for any pair of pwm signals is said to operate in full off when the desired hi side output of the three-phase timing unit is in the off state (hi) be- tween successive pwmsync pulses. this state may be entered by virtue of the commanded duty cycle values (in conjunction with the pwmdt register) or by virtue of the correct operation of the pulse deletion circuit. ? normal modulation: the pwm for any pair of pwm signals is said to operate in normal modulation when the desired output duty cycle is other than 0% or 100% between successive pwmsync pulses. there are certain situations when transitioning either into or out of either full on or full off where it is necessary to insert additional dead time delays to prevent potential shoot through conditions in the inverter. the particular situation also depends on whether operation is in single or double update mode. in double update mode, it is also necessary to consider whether the pwm unit is transitioning from the first half cycle to the second half cycle or vice versa. these transitions are detected automati- cally by the admc401 and, if appropriate, the dead time is inserted. the insertion of the additional dead time into one of the pwm signals of a given pair during these transitions is only needed if otherwise both pwm signals would be required to toggle at the pwmsync boundary. the additional dead time delay is in- serted into the pwm signal that is toggling into the on state. in effect the turn on of this signal is delayed by an amount 2 pwmdt t ck from the rising edge of pwmsync. after this delay, the pwm signal is allowed to turn on, provided the desired output is still the on state after the dead time delay. figure 24 illustrates two examples of such transitions where in figure 24(a) when transitioning from normal modulation to full on at the half cycle boundary in double update mode, no special action is needed. however, in figure 24(b) when transitioning into full off at the same boundary, it can be seen that an additional dead time is necessary. 2 pwmdt pwmcha 1 full on ah al 2 pwmdt full off ah al (a) (b) pwmtm pwmtm dead time inserted figure 24. examples of transitioning form normal modu- lation into either full on or full off where it may be nec- essary to insert additional dead times. minimum pulsewidth, pwmpd register in many power converter switching applications, it is desirable to eliminate pwm switching signals below a certain width. it takes a certain finite time to both turn on and turn off power semiconductor devices. therefore, if the width of any of the pwm signals goes below some minimum value, it may be desir- able to completely eliminate the pwm switching for that par- ticular cycle. the allowable minimum pulsewidth for any of the six pwm outputs that can be produced by the pwm controller may be programmed using the 10-bit pwmpd register. the minimum pulsewidth, t min , is programmed in increments of t ck as: t pwmpd t min ck = so that a pwmpd value of 0x00a defines a permissible mini- mum on time of 0.39 s for a 26 mhz clkout. the opera- tion of the minimum pulsewidth control ensures that the time from turning on to turning off (or alternatively from turning off to turning on) any pwm signal is never less than the t min value as specified by the pwmpd register. if the pwm controller detects that the time between turning on and turning off any one pwm signal (say ah) is less than t min , the pwm pulse is deleted and the pwm signal remains completely off over the pwm period. the complementary signal, al in this case, is then turned completely on. effective pwm resolution in single update mode, the same values of pwmcha, pwmchb and pwmchc are used to define the on-times in both half cycles of the pwm period. as a result, the effective resolution of the pwm generation process is 2t ck (or 77 ns for a 26 mhz clkout), since incrementing one of the duty cycle registers by one changes the resultant on-time of the associated pwm signals by t ck in each half period (or 2t ck for the full period). in double update mode, improved resolution is possible since different values of the duty cycles registers are used to define the on-times in both the first and second halves of the pwm period. as a result, it is possible to adjust the on-time over the whole period in increments of t ck . this corresponds to an effective pwm resolution of t ck in double update mode (or 38.5 ns for a 26 mhz clkout). the ac hievable pwm switching f requency at a given pwm resolution is tabulated in table iv. table iv. achievable pwm resolution in single and double update modes (clkout = 26 mhz) resolution single update mode double update mode (bits) pwm frequency (khz) pwm frequency (khz) 8 50.8 102 9 25.4 50.8 10 12.7 25.4 11 6.35 12.7 12 3.17 6.35 output control unit, pwmseg register the operation of the output control unit is controlled by the 9-bit read/write pwmseg register which controls two distinct features that are directly useful in the control of ecm or b dcm. crossover feature the pwmseg register contains three crossover bits; one for each pair of pwm outputs. setting bit 8 of the pwmseg regis- ter enables the crossover mode for the ah/al pair of pwm
rev. b admc401 C32C signals, setting bit 7 enables crossover on the bh/bl pair of pwm signals and setting bit 6 enables crossover on the ch/cl pair of pwm signals. if crossover mode is enabled for any pair of pwm signals, the high side pwm signal from the timing unit (ah say) is diverted to the associated low side output of the output control unit so that the signal will ultimately appear at the al pin. of course, the corresponding low side output of the timing unit is also diverted to the complementary high side output of the output control unit so that the signal appears at the ah pin. following a reset, the three crossover bits are cleared so that the crossover mode is disabled on all three pairs of pwm signals. output enable function the pwmseg register also contains six bits (bits 0 to 5) that can be used to individually enable or disable each of the six pwm outputs. the pwm signal of the al pin is enabled by setting bit 5 of the pwmseg register while bit 4 controls ah, bit 3 controls bl, bit 2 controls bh, bit 1 controls cl and bit 0 controls the ch output. if the associated bit of the pwmseg register is set, the corresponding pwm output is disabled irre- spective of the value of the corresponding duty cycle register. this pwm output signal will remain in the off state as long as the corresponding enable/disable bit of the pwmseg register is set. this output enable function is implemented after the cross- over function. following a reset, all six enable bits of the pwmseg register are cleared so that all pwm outputs are enabled by default. in a manner identical to the duty cycle registers, the pwmseg is latched on the rising edge of the pwmsync signal so that changes to this register only become effective at the start of each pwm cycle in single update mode. in double update mode, the pwmseg register can also be updated at the midpoint of the pwm cycle. brushless dc motor (electronically commutated motor) control in the control of an ecm only two inverter legs are switched at any time and often the high side device in one leg must be switched on at the same time as the low side driver in a second leg. therefore, by programming identical duty cycle values for two pwm channels (i.e., pwmcha = pwmchb) and setting bit 7 of the pwmseg register to crossover the bh/bl pair of pwm signals, it is possible to turn on the high side switch of phase a and the low side switch of phase b at the same time. in the control of ecm, it is usual that the third inverter leg (phase c in this example) be disabled for a number of pwm cycles. this function is implemented by disabling both the ch and cl pwm outputs by setting bits 0 and 1 of the pwmseg register. this situation is illustrated in figure 25, where it can be seen that both the ah and bl signals are identical, since pwmcha = pwmchb and the crossover bit for phase b is set. in addi- tion, the other four signals (al, bh, ch and cl) have been disabled by setting the appropriate enable/disable bits of the pwmseg register. for the situation illustrated in figure 25, the appropriate value for the pwmseg register is 0x00a7. in normal ecm operation, each inverter leg is disabled for certain periods of time, so that the pwmseg register is changed based on the position of the rotor shaft (motor commutation). ah al bh bl ch cl pwmtm pwmtm pwmcha = pwmchb pwmcha = pwmchb 2 pwmdt 2 pwmdt figure 25. example active lo pwm signals suitable for ecm control, pwmcha = pwmchb, crossover bh/bl pair and disable al, bh, ch and cl outputs. operation is in single update mode. gate drive unit, pwmgate register high frequency chopping the gate drive unit of the pwm controller adds features that simplify the design of isolated gate drive circuits for pwm invert- ers. if a transformer-coupled power device gate drive amplifier is used, the active pwm signal must be chopped at a high fre- quency. the 10-bit pwmgate register allows the program- ming of this high frequency chopping mode. the chopped active pwm signals may be required for the high-side drivers only, for the low side drivers only or for both the high side and low side switches. therefore, independent control of this mode for both high and low side switches is included with two separate control bits in the pwmgate register. typical pwm output signals with high frequency chopping enabled on both high side and low side signals are shown in figure 26. chopping of the high side pwm outputs (ah, bh and ch) is enabled by setting bit 8 of the pwmgate register. chopping of the low side pwm outputs (al, bl and cl) is enabled by setting bit 9 of the pwmgate register. the high frequency chopping frequency is controlled by the 8-bit word (gdclk) placed in bits 0 to 7 of the pwmgate register. the period of this high frequency carrier is: t gdclk t chop ck = + () [] 41 and the chopping frequency is therefore an integral subdivision of the clkout frequency: f f gdclk chop clkout = + () [] 41 the gdclk value may range from 0 to 255, corresponding to a programmable chopping frequency rate from 25.4 khz to 6.5 mhz for a 26 mhz clkout rate. the gate drive features must be programmed before operation of the pwm controller and typically are not changed during normal operation of the pwm controller. following reset, all bits of the pwmgate register are cleared so that high frequency chopping is disabled, by default.
admc401 C33C rev. b pwmtm pwmtm [4 (gdclk+1)] 2 pwmdt 2 pwmdt pwmcha pwmcha ah al figure 26. typical active lo pwm signals with high fre- quency gate chopping enabled on both high side and low side switches. pwm polarity control, pwmpol pin the polarity of the pwm signals produced at the output pins ah to cl may be selected in hardware by the pwmpol pin. connecting the pwmpol pin to dgnd selects active lo pwm outputs, such that a lo level is interpreted as a com- mand to turn on the associated power device. conversely, con- necting the pwmpol pin to v dd selects active hi pwm and the associated power devices are turned on by a hi level at the pwm outputs. there is an internal pull-up on the pwmpol pin, so that if this pin becomes disconnected (or is not connected), active hi pwm will be produced. the level on the pwmpol pin may be read from bit 2 of the sysstat register, where a zero indicates a measured lo level at the pwmpol pin. switched reluctance mode the pwm block of the admc401 contains a switched reluc- tance (sr) mode that is controlled by the pwmsr pin. the switched reluctance mode is enabled by connecting the pwmsr pin to dgnd. in this sr mode, the low side pwm signals from the three-phase timing unit assume permanently on states, independent of the value written to the duty-cycle registers. the duty cycles of the high side pwm signals from the timing unit are still determined by the three duty cycle registers. using the crossover feature of the output control unit, it is possible to divert the permanently on pwm signals to either the high-side or low-side outputs. this mode is necessary because in the typi- cal power converter configuration for sw itched or variable reluc- tance motors, the motor winding is connected between the two power switches of a given inverter leg. therefore, in order to build up current in the motor winding, it is necessary to turn on both switches at the same time. typical active lo pwm signals during operation in sr mode are shown in figure 27 for opera- tion in double update mode. it is clear t hat the three low-side signals (al, bl and cl) are perma nently on and the three high side signals are modulated in the usual manner so that the cor- responding high side power switches are switched between the on and off states. the sr mode can only be enabled by con- necting the pwmsr pin to gnd. there is no software means by which this mode can be enabled. there is an internal pull-up resistor on the pwmsr pin so that if this pin is left unconnected or becomes disconnected the sr mode is disabled. of course, the sr mode is disabled when the pwmsr pin is tied to v dd . pwmcha 1 pwmtm ah al bh ch bl cl pwmcha 2 pwmchb 2 pwmchb 1 pwmchc 2 pwmchc 1 pwmtm figure 27. active lo pwm signals in sr mode (pwmpol = pwmsr = dgnd) for admc401 in double update mode. pwm shutdown in the event of external fault conditions, it is essential that the pwm system be instantaneously shutdown in a safe fashion. a low level on the pwmtrip pin provides an instantaneous, asynchronous (independent of the dsp clock) shutdown of the pwm controller. all six pwm outputs are placed in the off state (as defined by the pwmpol pin). note, however, when the pwmsr pin is in the sr mode, the three low side pwm signals from the three-phase timing unit will remain in the on state. in addition, the pwms ync pulse is disabled and the associated interrupt is stopped. the pwmtrip pin has an internal pull-down resistor so that if the pin becomes uncon- nected the pwm will be disabled. the state of the pwmtrip pin can be read from bit 0 of the sysstat register. the 12 pio lines of the admc401 can also be configured to operate as pwm shutdown pins using the piopwm register. the 12-bit piopwm has a control bit for each pio line (bit 0 controls pio0, etc.). setting the control bit enables the corre- sponding pio line as a pwm shutdown pin. a falling edge on the pio line will then generate an instantaneous, asynchronous shutdown of the pwm system, in a manner identical to the pwmtrip pin. also like pwmtrip , all of the pio lines have internal pull-down resistors, so that if a pio pin becomes uncon- nected and is configured as a pwm shutdown pin, the pwm will be disabled. following a reset, all pio lines are configured as inputs, have pull-downs and are programmed as pwm shut down pins (piopwm = 0x0fff) so that the pwm is shut- down. correct operation of the pwm is not possible without first correctly configuring the pio system. in addition, it is possible to initiate a pwm shutdown in soft- ware by writing to the 1-bit pwmswt register. the act of writing to this register generates a pwm shutdown command in a manner identical to the pwmtrip or pio pins. a hardware trip has no effect on the pwmswt register. it does not matter which value is written to the pwmswt register. however, following a pwm shutdown, it is possible to read the pwmswt register to determine if the shutdown was generated by hard- ware or software. if the pwm shutdown was caused by the pwmswt register, a 1 will be read back from the pwmswt register. reading the pwmswt register automatically clears its contents.
rev. b admc401 C34C on the occurrence of a pwm shutdown command (either from the pwmtrip pin, the pio lines or the pwmswt register), a pwmtrip interrupt will be generated. in addition, the pwmsync pulse no longer appears at the output pin. how- ever, internal operation of the pwm timer continues. following a pwm sh utdown, the pwm can only be re-enabled (in a pwmtrip interrupt service routine, for example) by writing to all of the pwmtm, pwmcha, pwmchb and pwmchc registers. provided the external fault has been cleared and the pwmtrip or appropriate pio lines have returned to a hi level, the pwm controller will restart. pwm registers the pwm registers are described in at the end of this data sheet. the parameters of the pwm block for operation at 26 mhz are tabulated in table v. encoder interface unit overview of encoder interface unit the admc401 incorporates a powerful encoder interface to incremental shaft encoders, that are often used for position feedback in high performance motion control systems. the functional block diagram of the entire encoder interface system of the admc401 is shown in figure 28. the encoder interface unit (eiu) includes a 16-bit quadrature up/down counter, programmable input noise filtering of the encoder input signals and the zero markers, and has four dedi- cated pins on the admc401. the quadrature encoder signals (or alternatively, frequency and direction inputs) are applied at the eia and eib pins. in addition, two zero marker/strobe in- puts are provided on pins eiz and eis. these inputs may be used to latch the contents of the encoder quadrature counter into dedicated registers, eizlatch and eislatch, on the occurrence of external events at the eiz and eis pins. these events may be pro grammed to be either rising edge only (latch event) or rising edge if the encoder is moving in the forward direction and falling edge if the encoder is moving in the reverse direction (software latched zero marker functionality). the encoder interface unit incorporates programmable noise filtering on the four encoder inputs to prevent spurious noise pulses from adversely affecting the operation of the quadrature counter. the encoder interface unit operates at a clock frequency equal to the dsp instruction rate. the encoder interface unit operates correctly with encoder signals at frequencies of up to 4.33 mhz, corre- sponding to a maximum quadrature frequency of 17.3 mhz (assuming an ideal quadrature relationship between the input eia and eib signals). eetcnt(15 0) eiucnt(15 0) eiumaxcnt(15 0) eiuctrl(8 0) eiustat(7 0) eislatch(15 0) eizlatch(15 0) eiufilter(5 0) pulse decimator clock divider encoder event timer quadrature signal encoder interface block encoder loop timer timeout direction encoder event timer block eetdiv(15 0) eetstat(0) eett(15 0) eetdeltat(15 0) eetn(7 0) eiuscale (7 0) eiutimer (15 0) eiuperiod (15 0) eia 16-bit quadrature up/down counter encoder counter control eib eiz b a eis z s programmable noise filters figure 28. configuration of encoder interface system of admc401 the eiu may be programmed to use the zero marker on eiz to reset the quadrature encoder in hardware, if required. alterna- tively, the zero marker can be ignored and the encoder quadra- ture counter is reset according to the contents of a maximum count register, eiumaxcnt. there is also a single north marker mode available in which the encoder quadrature counter is reset only on the first zero marker pulse. both modes are enabled by dedicated control bits in the eiu control regis- ter, eiuctrl. a status bit is set in the eiustat register on the first occurrence of the zero marker. the encoder interface unit can also be made to implement some error checking functions. if the error checking mode is enabled, upon the occurrence of a zero pulse, the contents of the encoder counter register are compared with the expected value (0 or eiumaxcnt depending on the direction of rotation). if an encoder count error is detected, a status bit in the eiustat table v. fundamental characteristics of pwm generation unit of admc401 (clkout = 26 mhz) parameter test conditions min typ max unit counter resolution 16 bits edge resolution double update mode 38.5 ns t d programmable dead time 0 78.8 s dead time increments 77.0 ns t min programmable minimum pulsewidth 0 39.4 s minimum pulsewidth increments 38.5 ns f pwm pwm switching frequency 16-bit resolution 198 hz f pwm pwm switching frequency 1 8-bit resolution 102 khz t pwmsync pwmsync pulsewidth 38.5 9850 ns pwmsync pulsewidth increments 38.5 ns f chop gate drive chopping frequency 25.4 6500 khz note: higher switching frequencies are possible at reduced resolutions (i.e., 202.8 khz at 7 bits, 405.6 khz at 6 bits, etc.)
admc401 C35C rev. b register is set and an eiu count error interrupt is generated. an additional status bit is provided in the eiustat register that indicates the initialization state of the eiu. until the eiumaxcnt register is writ ten to, the eiu is not initialized. four status bits in the eiustat register provide the state of the four eiu inputs, eia, eib, eiz and eis. the encoder interface unit of the admc401 contains a 16-bit loop timer that behaves in a manner similar to the program- mable interval timer of the dsp core. the loop timer consist of a timer register, period register and scale register so that it can be programmed to timeout and reload at appropriate intervals. a control bit in the eiuctrl register is used to enable/disable this loop timer. when this loop timer times out, an eiu loop timer timeout interrupt is generated. this interrupt could be used to control the timing of speed and position control loops in high performance drives. the encoder interface unit also includes a high performance encoder event timer (eet) block that permits the accurate timing of successive events of the encoder inputs. the eet can be programmed to time the duration between up to 255 encoder pulses and can be used to enhance velocity estimation, particu- larly at low speeds of rotation. the information from the regis- ters of the eet block can be latched in two ways. in one mode, the contents of the eiu quadrature count register, eiucnt and all relevant eet registers (eett and eetdeltat) are latched when the eiu loop timer times out. in the second mode, the act of reading the eiucnt register also simultaneously latches the eet registers. the eet data latching mode is se- lected by a control bit in the eiuctrl register. encoder loop timer the eiu contains a 16-bit loop timer that is structured in a manner similar to the interval timer of the dsp core (tcount, tperiod and tscale registers). the corresponding regis- ters of the encoder loop timer are the 16-bit eiutimer and eiuperiod registers and the 8-bit eiuscale register. the eiu loop timer is clocked at the clkout rate, t ck . the eiu loop timer can be used to generate periodic interrupts based on multiples of the dsp cycle time. the eiu loop timer is enabled by setting bit 5 of the eiuctrl register. when enabled, the 16-bit timer register (eiutimer) is decremented every n cycles, where n-1 is the scaling value stored in the 8-bit eiuscale register. when the value of the eiutimer register reaches zero, the eiu loop timer timeout interrupt is generated and the eiutimer register is reloaded with the 16-bit value in the eiuperiod register. the scaling feature of this timer, provided by the eiuscale register, allows the 16-bit timer to generate periodic interrupts over a wide range of periods. for a 26 mhz clkout rate (38.5 ns period), the timer can gener- ate interrupts with periods of 38.5 ns up to 2.52 ms with a zero scale value (eiuscale = 0). when scaling is used, time peri- ods can range up to 0.645 sec. the eiu loop timer timeout interrupt can be masked in the picmask register. encoder interface structure and operation introduction the encoder interface section consists of a 16-bit quadrature up/down counter and a 16-bit eiucnt register that allows the up/down counter to be read by the dsp. there is also a 16-bit eiumaxcnt register that must be written to, to initialize the encoder system. until the eiumaxcnt register has been written to, the encoder interface unit is not initialized and bit 2 of the eiustat register is set. the contents of the eiumaxcnt register are used in certain operating modes to reset the quadrature counter. the contents of the eiumaxcnt register are also used for error checking of the eiu. operation of the encoder interface is controlled by the eiuctrl register. programmable input noise filtering of encoder signals a functional block diagram of the input stages of the encoder interface is shown in figure 29. the four encoder input signals (eia, eib, eiz and eis) are first synchronized in input syn- chronization buffers. this eliminates the asynchronous nature of real world encoder signals prior to use in the encoder interface unit logic. subsequently, all four synchronized signals (eias, eibs, eizs and eiss) are applied to programmable noise filter- ing circuits that can be programmed to reject pulses that are shorter than some suitable value. the outputs of the filter stage are applied to the quadrature counter stage. eia eib eiz eis clkout clock divide eiufilter(5 0) eias eibs eizs eiss a b z s three stage digital filter input synchroniza- tion stage figure 29. functional block diagram of input stage of encoder interface each of the four synchronized input signals (eias, eibs, eizs and eiss) is applied to a three clock cycle delay filter such that the filtered output signals are not permitted to change until a stable value has been registered for three successive clock cycles. while the encoder signals are changing, the filter maintains the previous output value. the clock frequency used for the filter circuits is programmed by bits 0 to 5 of the eiufilter regis- ter. the 6-bit quantity written to bits 0 to 5 of the eiufilter register is used to divide the clkout frequency and provide the clock source for the encoder noise filters. if the value written to bits 0 to 5 of the eiufilter register is n, the period of the clock source used in the encoder filters is (n + 1) t ck . this filter structure guarantees that encoder pulses of less width than 2 (n + 1) t ck will always be rejected by the filter stage. additionally, pulses greater than 3 (n + 1) t ck will always get through the filter stage and be passed to the internal quadra- ture counter. encoder pulses of widths between 2 (n + 1) t ck and 3 (n+1) t ck may either pass through or be rejected by the encoder filter. whether or not such pulses pass through the filter depends on the exact nature of the synchronization between the external asynchronous pulses and the internal dsp clock and is impossible to predict. for example, writing a value of 3 to the eiufi lter register, means that the clock frequency used in the encoder filters is 6.5 mhz (for a clkout rate of 26 mhz). in order to register as a stable value, the encoder input signals must be stable for three of these 6.5 mhz cycles (or 462 ns). consequently, the smallest period that will be registered on the synchronized en- coder inputs is 924 ns, corresponding to a maximum encoder
rev. b admc401 C36C rate of 1.08 mhz. in general, the maximum encoder rate that can be consistently recognized is given by: f f n encmax clkout = + 61 () operation of both the input synchronization logic and the noise filters is shown in f igure 30 for the default case where eiufilter(5::0) = 0x00 and the noise filters are clocked at clkout. clkout eia eib eias eibs a b 3t ck 3t ck noise pulse 1t ck figure 30. operation of input synchronization and noise filters of encoder interface with eiufilter(5:0) = 0x00 such that the filters are operated at clkout. the default value for eiufilter(5::0) following a power on or reset is 0x00 so that the eiu filters are clocked at the clk- out rate and minimal filtering is applied. there is a direct trade-off between the amount of filtering applied to the encoder inputs and the maximum possible encoder signal rate. in effect, the larger the value of eiufilter(5::0), the more filtering that is applied to the encoder signals, so that, for a given number of encoder lines, the maximum speed of rotation is lower. the influence of the encoder filter on the zero marker signals (eiz and eis) can be somewhat different that on the eia or eib signals, depending on the exact nature of the encoder. in common incremental encoders, the width of the zero marker can be equal to a quarter, a half or a full period of one of the quadrature signals (say eia). applying the three-stage delay filter to a zero marker whose width is either equal to half or a full quadrature pulse period does not change the achievable maximum encoder rate. however, the maximum possible en- coder rate is changed if the three-stage filter is applied in the case where the width of the zero marker is equal to a quarter of the eia or eib period. in this case the influence of the three- stage delay filter is to effectively half the maximum encoder signal rate to that described above (or 2.15 mhz for a 26 mhz clkout rate). encoder counter direction the direction of quadrature counting is determined by bit 0 (rev) of the eiuctrl register. if the rev bit is cleared, the signal at the eia pin is fed to the a input to the quadrature counter and the eib pin is fed to the b input. thus, if the eia- encoder signal leads the eib-signal (and therefore the a signal leads the b signal), the quadrature counter is incremented on each edge. this (a signal leads the b signal) is defined as the forward direction of motion . setting bit 0 of the eiuctrl regis- ter causes the signal at the eia pin to be fed to the b input to the quadrature counter and the signal eib becomes the a input to the quadrature counter. therefore, if the eia signal led the eib signal at the pins of the admc401, the a input to the quadrature counter will now lag the b input. this will be recog- nized as rotation in the reverse direction and the counter will be decremented on each quadrature pulse. following a reset, the rev bit is cleared. the two encoder signals are used to derive a quadrature signal that is used, in conjunction with a direction bit, to increment or decrement the encoder counter and also the encoder event timer. the status of the direction signal is indicated at bit 1 of the eiustat register. while the encoder counter is incre- menting, bit 1 is set. alternatively, when the encoder counter is decrementing, bit 1 of the eiustat register is cleared. alternative frequency and direction inputs instead of the quadrature eia and eib encoder inputs, the encoder interface unit can also accept alternative frequency and direction inputs. this mode is enabled by setting bit 6 of the eiuctrl register. in this so-called fd mode , the eia input pin accepts a frequency signal and the eib pin accepts the di- rection signal. the signal on these pins are subject to the same synchronization and filtering logic as described previously. how- ever, in this mode the quadrature counter is incremented or decremented on both the falling and rising edges of the signal on the eia pin. if the eib pin is lo, forward operation is as- sumed and the counter is incremented on each edge of the fre- quency signal on the eia input. on the other hand, if the eib pin is hi, reverse rotation is assumed and the quadrature counter is decremented at each edge of the signal on the eia pin. on power-up or reset, bit 6 of the eiuctrl register is cleared so that this mode is disabled by default. the following modes are not supported when fd mode is enabled: encoder counter reset mode, single north marker mode, and encoder error checking mode. in other words, when bit 6 of eiuctrl is set, bits 1, 2, and 3 should be cleared. encoder counter reset the zero bit (bit 1) of the eiuctrl register determines if the encoder zero marker is used to hardware reset the up/down counter of the encoder interface. when bit 1 of the eiuctrl register is set, the zero marker signal on the eiz pin is used to reset the up/down counter to zero (if moving in the forward direction) or to the value in the eiumaxcnt register (if mov- ing in the reverse direction). the reset operation takes place on the next quadrature pulse after the zero marker has been recog- nized. in order to ensure correct encoder counting (no missing or spurious codes) the logic in the encoder counter latches the conditions (appropriate encoder edge) at which the first reset is performed. thereafter, irrespective of operating conditions, the encoder reset operation is always aligned with the same encoder edge. for example, if the first reset operation occurs on the rising edge of b and the encoder is moving in the forward direc- tion, then all subsequent reset operations are aligned with the rising edge of the b signal (while moving in the forward direc- tion) and on the falling edge of b for rotation in the reverse direction. in order to account for zero marker signals of differ- ent widths, the zero marker will be recognized as the rising edge of the eiz signal when moving in the forward direction. when
admc401 C37C rev. b moving in the reverse direction, the zero marker is recognized at the falling edge of the signal at the eiz pin. when the zero bit of the eiuctrl register is cleared, the zero marker is not used to reset the counter. in this mode, the contents of the eiumaxcnt register are used as the reset value for the up/down counter. for example, for an n-line incremental encoder, the appropriate value to write to the eiumaxcnt register is 4nC1. therefore, for a 1024 line encoder, a value of 0x0fff (= 4095) would be written to the eiumaxcnt register. however, since absolute position infor- mation is not available in this mode, due to the absence of the zero marker, the full 16-bit range of the quadrature counter may be employed by writing a value of 0xffff to the eiumaxcnt register. following a reset, the zero bit is cleared. the value written to the eiumaxcnt register must be in the form 4nC1, where n is any integer. registration inputs and software zero marker the encoder interface unit of the admc401 provides two marker signals, eiz and eis that are both filtered and synchro- nized in a manner identical to the other encoder signals to pro- duce the z and s signals. z can be used as a hardware reset of the encoder counter, as described above. however, in many applications a hardware reset of the counter may not be desir- able. instead, the encoder counter can be programmed to operate in full 16-bit roll-over mode, by clearing bit 1 of the eiuctrl register and programming eiumaxcnt to be 0xffff. in this case, the quadrature counter will use the full 16-bit range of the eiucnt register. the signals on z and s can be configured to latch the contents of the eiucnt register into dedicated memory mapped regis- ters (eizlatch for the z signal and eislatch for the s signal) on the occurrence of definite events on these pins. the exact nature of the events are determined by bit 7 of the eiuctrl register for the z input and bit 8 of the eiuctrl register for the s signal. if bit 7 of the eiuctrl register is cleared, the contents of the eiucnt register are latched to the eizlatch register on the occurrence of a rising edge on the z signal. in this mode, the signals can be used to latch or freeze the eiucnt contents on the occurrence of an external event such as that from limit switches or other triggers. if bit 7 of the eiuctrl register is set, then the eiucnt contents are latched to the eizlatch register on the occurrence of the next quadrature pulse following the rising edge of the z signal if the quadrature counter is incre- menting (count up). if the quadrature counter is decrementing, the eiucnt contents are latched to the eizlatch register on the next quadrature pulse following the falling edge of the z signal. in this mode, the action resembles that of a zero marker function. the advantage is that the eiucnt register contents are latched at the appropriate zero marker inputs, but the con- tents of the quadrature counter are not affected. bit 8 of the eiuctrl register defines the s events that cause the eiucnt register to be latched to the eislatch register. when bit 8 of the eiuctrl register is cleared, the contents of the eiucnt register are latched to the eislatch register on the occurrence of a rising edge on the s signal, in a manner identical to that for the z input. if bit 8 of the eiuctrl regis ter is set, the operation is slightly different to that for the z input. with the s input, the eiucnt contents are latched to the eislatch register on the occurrence of a rising edge of the s signal if the quadrature counter is incrementing (count up). if the quadrature counter is decrementing, the eiucnt contents are latched to the eislatch register on the occur- rence of the falling edge of the s signal. the difference is that the latching occurs at the event on the s input and not at the next quadrature event (as with this case on the z input). eizlatch and eislatch are 16-bit read-only registers whose state is undefined on power-up. on power-up or follow- ing a reset, both bits 7 and 8 of the eiuctrl register are cleared. single north marker mode a further reset mode, called single north marker mode, is avail- able in the encoder interface unit . this mode is enabled by setting bit 2 (snm) of the eiuctrl register. for this mode to operate the zero bit (bit1) of the eiuctrl register must also be set. in this mode, the eiucnt register is reset (to zero or eiumaxcnt, depending on direction) only on the first occurrence of the zero marker. subsequently, the eiucnt register is reset by the natural roll-over to zero or the value in the eiumaxcnt register. following a reset, this snm bit is cleared. bit 7 of the eiustat register is used to signal the first occurrence of a zero marker. when the first zero marker has been recognized by the eiu, bit 7 of the eiustat register is set. encoder error checking error checking in the eiu is enabled by setting bit 3 (mon) of the eiuctrl register. to be enabled, the zero bit of the eiuctrl register must also be set for error checking. in this mode, the contents of the eiucnt register are compared with the expected value (zero or eiumaxcnt depending on direc- tion) when the zero marker is detected. if a value other than the expected value is detected, an error condition is generated by setting bit 0 of the eiustat register and triggering an eiu count error interrupt. this eiu count error interrupt is man- aged and may be masked by the programmable interrupt con- troller (pic) block. the encoder continues to count encoder edges after an error has been detected. bit 0 of the eiustat register is cleared on the occurrence of the next zero marker provided the error condition no longer exists and the eiucnt register again matches the expected value. following a reset, the mon bit is cleared. encoder input status four additional status bits are provided in the eiustat regis- ter that provide a measure of the state of the four eiu inputs following the synchronization buffers and input filter. bit 3 indi- cates the state of the eia signal, bit 4 indicates the state of the eib signal, bit 5 gives the state of the eiz signal and bit 6 gives the state of the eis signal. the value of these status bits read is not affected by any of the control bits in the eiuctrl register. encoder event timer introduction and overview the encoder event timer block forms an integral part of the eiu of the admc401, as shown in figure 28. the eet accurately times the duration between encoder events. the information provided by the eet may be used to make allowances for the
rev. b admc401 C38C asynchronous timing of encoder and dsp-reading events. as a result, more accurate computations of the position and velocity of the motor shaft may be performed. the eet consists of a 16-bit encoder event timer, an encoder pulse decimator and a clock divider. the eet clock frequency is selected by the 16-bit read/write eetdiv clock divide register, whose value divides the clkout frequency. the contents of the encoder event timer are incremented on each rising edge of the divided clock signal. an eetdiv value of zero gives the maximum divide value of 0x10000 (= 65,536), so that the clock frequency to the encoder event timer is at its minimum possible value. the quadrature signal from the encoder interface unit is deci- mated at a rate determined by the 8-bit read/write eetn regis- ter. for example, writing a value of two to eetn, produces a pulse decimator output train at half the quadrature signal fre- quency, as shown in figure 31. the rising edge of this deci- mated signal is termed a velocity event. therefore, for an eetn value of two, a velocity event occurs every two encoder edges, or on each edge of one of the encoder signals. an eetn value of 0 gives an effective pulse decimation value of 256. on the occurrence of a velocity event, the contents of the en- coder event timer are stored in an intermediate interval time register. under normal operation, this register stores the elapsed time between successive velocity events. after the timer value has been latched at the velocity event, the contents of the en- coder event timer are reset to one. encoder event timer value eet latch event velocity events quadrature signal eiucnt b a eett eetdeltat figure 31. operation of encoder interface unit and eet of admc401 in the forward direction with eetn = 2 latching data from the eet when using the data from the encoder event timer, it is im- portant to latch a triplet set of data at the same instant in time. the three pieces of data are the contents of the encoder quadra- ture up/down counter, the stored value in the interval time register (giving the precise measured time between the last two velocity events) and the present value of the encoder event timer (giving an indication of how much time has passed since the last velocity event). the data from the eet can be latched on the occurrence of two different events. the particular event is selected by bit 4 (eetlatch) of the eiuctrl register. setting this eetlatch bit causes the data to be latched on the timeout of the encoder loop timer (eiutimer). at that time, the contents of the encoder quadrature counter (eiucnt) are latched to a 16-bit register eetcnt. in addition, the contents of the inter- mediate interval time register are latched to the eett register and the contents of the encoder event timer are latched to the eetdeltat register. the three registers, eetcnt, eett and eetdeltat, then contain the desired triplet of position/ speed data required for the control algorithm. in addition, if the timeout of the eiutimer is used to generate an eiu loop timer interrupt, the required data is automatically latched and waiting for execution of the interrupt service routine (which may be some time after the timeout instant if there are multiple interrupts in the system). by latching the eiucnt register to the eetcnt, the user does not have to worry about changes in the eiucnt register (due to additional encoder edges) prior to servicing of the eiu loop timer interrupt. the other eet latch event is defined by clearing the eetlatch bit of the eiuctrl register. in this mode, whenever, the eiucnt register is read by the dsp, the current value of the interm ediate interval time register is latched to the eett register and the contents of the encoder event timer are latched to the eetdeltat register. the three registers, eiucnt, eett and eetdeltat now contain the desired triplet of position/speed data required for the control algorithm. note the difference from before, in that the encoder count value is now available in the eiucnt register. it is important to realize that the eett, and eetdeltat regis- ters are only updated by either the timeout of the eiutimer register (if eetlatch bit is set) or the act of reading the eiucnt register (if the eetlatch bit is cleared). theref ore, if the eetlatch bit is set, the act of reading the eiucnt register will not update the eett and eetdeltat registers. following reset, bit 4 of the eiuctrl is cleared. eet status register there is a 1-bit eetstat register that indicates whether or not an overflow of the eet has occurred. if the time between successive velocity events is sufficiently long, it is possible that the encoder event timer will overflow. when this condition is detected, bit 0 of the eetstat register is set and the eett register is fixed at 0xffff. reading the eetstat register clears the overflow bit and permits the eett register to be updated at the next velocity event. if an encoder direction reversal is detected by the eiu, the encoder event timer is set to 1 and the eett register is set to its maximum 0xffff value. subsequent velocity events will cause the eett register to be updated with the correct value. if a value of 0xffff is read from the eett register, bit 0 of the eetstat register can be read to determine whether an over- flow or direction reversal condition exists. on reset the eetn, eetdiv, eetdeltat and eett regis- ters are all cleared to zero. whenever either the eetn or eetdiv registers are written to, the encoder event timer is reset to zero and the eett register is set to zero.
admc401 C39C rev. b eiu/eet registers the structure and functionality of the eiu and eet registers are illustrated at the end of the data sheet. the characteristics of the eiu block at 26 mhz are given in table vi. programmable digital input/output overview the admc401 has 12 programmable digital input/output pins called pio0 to pio11. each pin may be individually configured as either an input or an output. an associated data register may be used to read data from pins configured as inputs and write data to pins configured as outputs. in addition, each i/o line may be configured as an interrupt source. both edge (rising and falling) and level (high and low) interrupts may be detected. four of the pio lines (pio0 to pio3) have dedicated vector addresses in the interrupt table. the remaining eight interrupts (pio4 to pio11) are multiplexed into a single additional inter- rupt vector location. the pioflag register is used to deter- mine which line caused the interrupt. in addition, all pio lines may be alternatively configured as pwm trip sources. the piopwm register has dedicated bits that may be used to enable this function on each pio line. in this mode, a low level on any pins configured as a pwm trip source shuts down the pwm in a manner identical to the pwmtrip pin. pio configuration each of the 12 programmable input/output lines may be config- ured as either an input or an output by programming the appro- priate bits of the piodir register. this 12-bit register has one bit associated with each i/o line; bit 0 corresponds to pio0, etc. clearing a bit in the piodir register will configure the corre- sponding pin as an input line. conversely, setting a bit config- ures the pin as an output pin. on reset, all bits of the piodir register are cleared so that all 12 pio pins are configured as inputs. in addition, all pio lines have internal pull-down resistors in the admc401 so that unconnected lines are seen as low level inputs. pio data reading/writing associated with the pio system is a data register, piodata, that also has a bit associated with each i/o line. data written to the piodata register will appear on those pins configured as outputs. reading the piodata register will read the data from those pins configured as inputs. pio interrupt generation each of the 12 pio lines may be configured as an interrupt source. four of the pio lines, pio0 to pio3, have dedicated interrupt vector locations, whereas the remaining eight are mul- tiplexed into an additional interrupt vector. the piointen register is used to enable or disable the interrupt mode on the pio4 to pio11 lines. the picmask register of the program- mable interrupt controller is used to enable interrupts on the four dedicated pio lines, pio0 to pio3, and to enable the usage of piointen for interrupts on the other pios. interrupts may be generated on either edge (rising or falling) or level (high or low) events by programming the appropriate bits of both the piomode and piolevel registers. both registers have a dedicated bit for each of the twelve pio lines. setting the appropriate bit of the piomode register configures the inter- rupt as level sensitive whereas clearing the bit configures the interrupt for edge sensitive. in level-sensitive mode (piomode bit is 1), setting the corresponding bit in the piolevel regis- ter configures the interrupt as active high, whereas clearing the bit configures it for active low. in edge-sensitive mode (piomode bit is 0), setting the corresponding bit of the piolevel register configures the interrupt for rising edge, whereas clearing the bit configures the interrupt for falling edge. on reset, all pio inter- rupts are disabled. the four dedicated pio interrupts from pio0 to pio3 have interrupt vector addresses at program memory addresses 0x0048 for pio0, 0x004c for pio1, 0x0050 for pio2 and 0x0054 for pio3. in the event of an interrupt on pio4 to pio11, the corre- sponding bit of the pioflag register is set and the general pio interrupt is activated. this interrupt has a dedicated vector address at location 0x003c. in the interrupt service routine for this interrupt, the user must poll the pioflag register to de- termine which of the pio4 to pio11 lines, that have interrupts enabled, caused the interrupt. of course, if only one of the pio4 to pio11 lines has interrupts enabled, no polling is necessary. pio lines that are configured as outputs may also be used to generate interrupts. if, for example, one of the pio lines is con- figured simultaneously as an output and as an interrupt source, writing the appropriate data sequence to that line will trigger an interrupt. pio as pwmtrip sources by setting the appropriate bits of the piopwm register, each of the twelve pio lines can be configured as a pwm shutdown source. in this mode, a low level on the pio pin will cause a pwm shutdown command that will disable all six pwm out- puts on ah to cl. since the disabling of the pwm is indepen- dent of the dsp clock, so that the pwm stage can be fully protected e ven in the event of a loss of clock signal to the dsp. in addition, a pwmtrip interrupt will be generated when the pwm is shutdown. however, it is also possible to generate the normal pio interrupts on the occurrence of a falling-edge on the pio line. the advantage of this highly flexible structure for pwm shutdown is that multiple fault signals could be applied to the admc401 at different pio lines. the occurrence of a falling- table vi. fundamental characteristics of encoder interface unit of admc401 (at 26 mhz) parameter test conditions min typ max unit f enc encoder input (eia, eib) rate 4.33 mhz f quad quadrature rate 17.3 mhz encoder loop timer timeout rate 38.5 ns 0.645 sec t minenc minimum encoder pulsewidth eiufilter = 0x00 116 ns eiufilter = 0x3f 7.39 s
rev. b admc401 C40C edge on any of them will instantaneously shut down the pwm. however, based on the particular pio interrupt that is flagged, the user can easily determine the source of the shutdown. this permits the action of the interrupt service routines following a pwm shutdown to be tailored to the particular fault that occurred. on reset, all pio lines are configured as pwm shutdown sources. because all pio lines are also configured as inputs and have internal pull-down resistors, any unconnected pio lines will cause a pwm shutdown. t herefore, prior to using the pwm system of the admc401, it is imperative that the pio stage be correctly configured for the particular application. pio registers the configuration of all registers associated with the pio system of the admc401 are shown at the end of the data sheet. each of the registers has a bit directly associated with one of the pio lines. for example, bit 0 of all registers affects only the pio0 line of the admc401. event timers overview the admc401 contains a dual channel event timer (capture) unit (etu) that may be used to accurately measure the elapsed time between defined instants on a particular channel. the etu has two dedicated input pins, etu0 and etu1. the etu system contains a set of 16-bit data registers that are used to store the value of the dedicated etu timer on the occurrence of defined events on the input pins. a configuration register is used to define the nature of the events on each of the input pins. in addition, a control register is used to initiate event capture on the inputs. a status register may be read to determine the state of the two capture channels. a dedicated etu interrupt may be generated upon completion of a capture sequence on either the etu0 or etu1 channels. an event may be defined as either a rising or falling edge on the associated etu0 and etu1 input pins. therefore, the etu system can be used to compute the frequency, period, duty cycle or on-time of signals applied at the inputs. a block diagram of the etu system of the admc401 is shown in figure 32. etua0(15 0) etub0(15 0) etuaa0(15 0) etudivide(15 0) etutime(15 0) etuconfig(7 0) etuctrl(1 0) etustat(1 0) etua1(15 0) etub1(15 0) etuaa1(15 0) capture channel 0 etu timer event detector event detector capture channel 1 etu0 etu1 figure 32. functional block diagram of event timer unit of admc401 etu event definition the etu system of the admc401 contains a dedicated 16-bit timer whose clock frequency may be programmed using the etudivide register. this register divides the clkout frequency to provide the clock signal for the etu timer. the clock frequency of the etu timer may be expressed as f clkout /etudivide and is common to both channels. at any time, the contents of the etu timer may be read in the 16-bit read only etutime register. two events are used to trigger the etu, termed event a and event b. by setting the appropriate bits of the etuconfig register, it is possible to define both events a and b as either rising or falling edges on the appropriate pin. for example, setting bit 0 of the etuconfig register defines event a of the etu0 channel as a rising edge on the etu0 pin. similarly, setting bit 4 of the etuconfig register defines event a of the etu1 channel as a rising edge on the etu1 pin. event a defines the start of the event capture sequence. associated with each etu channel are three data registers, etua0, etub0 and etuaa0 for etu channel 0 and etua1, etub1 and etuaa1 for etu channel 1. these data registers store the etu timer value on the occurrence of the first a event, the first b event and the second a event, respectively. for example, for etu channel 0, etua0 stores the timer value on the first occurrence of event a on the etu0 pin, etub0 stores the timer value on the first occurrence of event b on the etu0 pin and etuaa0 store the timer value on the second occurrence of event a on the etu0 pin. registers etua1, etub1 and etuaa1 perform the same function for events on etu channel 1. etu interrupt generation the completion of the event capture sequence can be defined as either the occurrence of event b or the second occurrence of event a by setting the appropriate bits of the etuconfig register. at the end of the capture sequence, the etu generates an interrupt. for example, if bit 2 of the etuconfig register is set, etu channel 0 will generate an etu interrupt on the occurrence of event b on the etu0 pin. on the other hand, if bit 6 of the etuconfig register is cleared, etu channel 1 will generate an etu interrupt on the occurrence of the second event a on the etu1 pin. both etu channels generate the same interrupt to the dsp when capture is complete. if both etu channels are used simultaneously, the etustat register can be polled to determine the status of both channels and determine which caused the interrupt. if capture on etu chan- nel 0 is complete, bit 0 of the etustat register is set. simi- larly, if event capture on etu channel 1 is complete, bit 1 of the etustat register is set. reading the etustat register automatically clears all bits of the register. etu operating modes the etu channels of the admc401 can operate in two dis- tinct modes; single shot and free-running. the particular mode may be selected for etu channel 0 by programming bit 3 of the etuconfig register and for etu channel 1 by program- ming bit 7 of the etuconfig register. setting these bits puts the respective etu channel in free-running mode while clearing the bits enables the single-shot mode. in single-shot mode, upon completion of the capture sequence and consequent generation of the interrupt, further event capture is disabled until the inter- rupt has been serviced and the appropriate bit of the etuctrl register has been set. setting bit 0 of the etuctrl register restarts the capture for etu channel 0, while bit 1 restarts capture for channel 1. in the free-running mode, the bits of the etuctrl register remain set and the etu channel continues to capture following the generation of the interrupt.
admc401 C41C rev. b etu registers the configuration of the etu registers is shown at the end of the data sheet. auxiliary pwm timers the admc401 provides two variable-frequency, variable duty- cycle, 8-bit, auxiliary pwm outputs that are available at the aux1 and aux0 pins. these auxiliary pwm outputs can be used to provide switching signals to other circuits in a typical motor control system such as power factor corrected front-end converters or other switching power converters. alternatively, by addition of a suitable filter network, the auxiliary pwm out- put si gnals can be used as simple single-bit digital-to-analog converters. the auxiliary pwm system of the admc401 can operate in two different modes, independent mode or offset mode . the oper- ating mode of the auxiliary pwm system is controlled by bit 8 of the modectrl register. setting bit 8 of the modectrl register places the auxiliary pwm system in the independent mode. in this mode, the two auxiliary pwm generators are completely independent, and separate switching frequencies and duty cycles may be programmed for each auxiliary pwm out- put. in this mode, the 8-bit auxtm0 register sets the switch- ing frequency of the signal at the aux0 output pin. similarly, the 8-bit auxtm1 register sets the switching frequency of the signal at the aux1 pin. the fundamental time increment for the auxiliary pwm outputs is twice the dsp instruction rate (or 2t ck ) so that the corresponding switching periods are given by: t auxtm t t auxtm t aux ck aux ck 0 1 201 211 = + = + () () since the values in both auxtm0 and auxtm1 can range from 0 to 0xff, the achievable switching frequency of the auxil- iary pwm signals may range from 50.8 khz to 13 mhz for a clkout frequency of 26 mhz. the on-time of the two auxiliary pwm signals are programmed by the two 8-bit auxch0 and auxch1 registers, according to: t auxch t t auxch t on aux ck on aux ck , , 0 1 20 21 = = so that output duty cycles from 0% to 100% are possible. duty cycles of 100% are produced if the on-time value exceeds the period value. typical auxiliary pwm waveforms in independent mode are shown in figure 33(a). when bit 8 of the modectrl register is cleared, the auxiliary pwm channels are placed in offset mode. in offset mode, the switching frequency of the two signals on the aux0 and aux1 pins are identical and controlled by auxtm0 in a manner similar to that previously described for independent mode. the on-times of both the aux0 and aux1 signals are controlled by the auxch0 and auxch1 registers as before. however, in this mode, the auxtm1 register defines the offset time from the rising edge of the signal on the aux0 pin to that on the aux1 pin, according to: t auxtm t offset ck = + 211 () for correct operation in this mode, the value written to the auxtm1 register must be less than the value written to the auxtm0 register. typical auxiliary pwm waveforms in offset mode are shown in figure (33)b. again, duty cycles from 0% to 100% are possible in this mode. in both operating modes, the resolution of the auxiliary pwm system is 8-bit only at the minimum switching frequency (auxtm0 = auxtm1 = 255 in independent mode, auxtm0 = 255 in offset mode). obviously, as the switching frequency is increased, the resolution is reduced. values can be written to the auxiliary pwm registers at any time. however, new duty cycle values written to the auxch0 and auxch1 registers only become effective at the start of the next cycle. writing to the auxtm0 and auxtm1 registers causes the internal timers to be reset to 0 and new pwm cycles to begin, only in independent mode. by default, following reset, bit 8 of the modectrl register is cleared and offset mode is enabled. auxtm0 and auxtm1 default to 0xff corresponding to minimum switch- ing frequency and zero offset. the on-time registers auxch0 and auxch1 default to 0x00. 2 auxch0 2 auxch0 (a) (b) aux0 aux1 aux0 aux1 2 (auxtm0+1) 2 (auxtm1+1) 2 auxch1 2 (auxtm0+1) 2 (auxtm1+1) 2 (auxtm0+1) 2 auxch1 figure 33. typical auxiliary pwm signals in (a) indepen- dent mode and (b) offset mode auxiliary pwm registers the registers of the auxiliary pwm system are illustrated at the end of the data sheet.
rev. b admc401 C42C watchdog timer overview the watchdog timer is used as a protection mechanism against unintentional software events causing the dsp to become stuck in infinite loops. it can be used to cause a complete dsp and peripheral reset in the event of such a software error. the watch- dog timer consists of a 16-bit timer that is clocked at the clkin rate, t cki . the watchdog timer is disabled after a master reset ( reset = lo). this also resets the wdflag bit in the sysstat regis- ter. the watchdog t imer is enabled by writing a timeout value to the wdtimer register. once the watchdog timer has been initialized, the timer is decremented at the clkin rate. in order to prevent a watchdog timer trip, it is necessary to write again to the wdtimer register. for all writes to the wdtimer register (subsequent to the initial write), it is unimportant which value is written. the act of writing to the wdtimer register automatically reloads the initial timeout value. if the watch- dog timer is not rewritten to after an interval: t wdt = wdtimer t cki the watchdog timer will decrement to zero and a watchdog trip will be generated. in this case, a complete reset of the dsp core and motor control peripherals (except the watchdog timer itself) is initiated and bit 1 of the sysstat register (wdflag) is set. following a reset, the dsp core can determine if the reset was caused by a watchdog trip (and if so take appropriate ac- tion) or if it was due to the normal reset sequence. the watchdog timer remains disabled while the wdflag is set to prevent continuous watch dog trips. the watchdog timer can be restarted and the wdflag reset by writing a nonzero timeout value to the wdtimer register. the wdflag will be reset, but the watchdog timer will remain disabled if 0x0000 is written to the wdtimer register. the watchdog timer is only reset by a low input on the reset pin. the watchdog circuit is not reset by a software controlled peripheral reset. programmable interrupt controller overview the admc401 uses the irq2 pin of the dsp core to generate a peripheral interrupt. there are multiple sources of peripheral interrupts, e.g., the adc block, pio block, eiu block, etu block and pwm block. a programmable interrupt controller (pic) is used to avoid a software latency in determining the source of the interrupt. with the occurrence of an interrupt from the peripheral blocks, the pic block generates an address that points to the corresponding vector address in the dsp vector table. the pic consists of an output register, picvector, that contains a pointer to an entry in the dsp vector table. during normal operation, an interrupt service routine (isr) located at vector address 0x0004 (or the irq2 /peripheral inter- rupt) jumps to the address pointed to by the picvector register. the necessary code to perform this jump from address 0x0004 is automatically placed there by the internal rom code when mmap = bmode = 1. the vector addresses between 0x00 and 0x2c are reserved for the dsp core interrupts. the vector table addresses from pm(0x30) to pm(0x58) are reserved for use by peripheral inter- rupt service routines. each vector address occupies four ad dresses of pm. the priority of the peripheral interrupts is fixed in hard- ware. the isr at address pm(0x30) has the highest priority whereas the isr at address pm(0x58) has the lowest. in the case of multiple simultaneous interrupts, the pic will load the picvector register with the interrupt that has the highest priority. between reads of the picvector register (while the dsp is servicing other interrupts for example) picvector is updated with the highest priority of any periph- eral interrupts. this ensures that when the irq2 is reasserted, the highest priority interrupt that occurred since the last reading of the picvector register is now waiting to be serviced. when picvector is read, if another interrupt is pending in the pic, then the irq2 line to the dsp remains lo and no edge will be seen. in order to catch all interrupts, irq2 interrupts should be configured as level sensitive in the icntl register. the four least significant pio pins are assigned unique vector addresses. an interrupt on any of the remaining eight lines (pio4 to pio11) will trigger a separate fifth pio interrupt that has its own vector address. the pioflag register can be read to determine the exact source of this fifth interrupt. an 11-bit picmask register can be used to enable or disable any or all of the eleven peripheral interrupt sources. the program memory address reserved for each of the interrupts is summarized in table vii. table vii. interrupt vector addresses function vector address reset startup (or power up with pucr = 1) 0x00 (highest priority) power-down (nonmaskable) 0x2c adc end-of-conversion interrupt 0x30 pwmsync interrupt 0x34 eiu loop timer timeout interrupt 0x38 pio4 to pio11 interrupt 0x3c eiu counter error interrupt 0x40 etu interrupt 0x44 pio0 interrupt 0x48 pio1 interrupt 0x4c pio2 interrupt 0x50 pio3 interrupt 0x54 pwm trip interrupt 0x58 sport0 transmit 0x10 sport0 receive 0x14 software interrupt 1 0x18 software interrupt 0 0x1c sport1 transmit (or irq1 ) 0x20 sport1 receive (or irq0 ) 0x24 interval timer interrupt 0x28 (lowest priority) interrupt masking interrupt masking (or disabling) is controlled by the imask register of the dsp core and the picmask register. these registers contain individual bits that must be set to enable the various interrupt sources. it is important to remember that if any peripheral interrupt is to be enabled both the irq2 interrupt enable bit (bit 9) of the imask register and the appropriate bit of the picmask register must be set. the configuration of both the imask and picmask registers of the admc401 is shown at the end of the data sheet.
admc401 C43C rev. b interrupt configuration the ifc and icntl registers of the dsp core control and configure the interrupt controller of the dsp core. the ifc register is a 16-bit register that may be used to force and/or clear any of the eight dsp interrupts. bits 0 to 7 of the ifc register may be used to clear the dsp interrupts while bits 8 to 15 can be used to force a corresponding interrupt. writing to bits 11 and 12 in ifc is the only way to create the two software interrupts. the icntl register is used to configure the sensitivity (edge or level) of the irq0 , irq1 and irq2 interrupts and to enable/ disable interrupt nesting. setting bit 0 of icntl configures the irq0 as edge sensitive while clearing the bit configures it for level sensitive. bit 1 is used to configure the irq1 interrupt and bit 2 is used to configure the irq2 interrupt. it is recommended that the irq2 interrupt be always configured for level sensitive as this ensures that no peripheral interrupts are lost. setting bit 4 of the icntl register enables interrupt nesting. the configura- tion of both ifc and icntl registers is shown at the end of the data sheet. interrupt operation following a reset (with romenable = 1), the rom code monitor of the admc401 copies a default interrupt vector table into program memory ram from address 0x0000 to 0x005f. since each interrupt source has a dedicated four word space in this vector table, it is possible to code short interrupt service routines (isr) in place. alternatively, it may be required to insert a jump instruction to the appropriate start address of the interrupt service routine if more memory is required for the isr. on the occurrence of an interrupt, the program sequencer en- sures that there is no latency (beyond synchronization delay) when processing unmasked interrupts. in the case of the timer, sport0, sport1 and software interrupts, the interrupt con- troller automatically jumps to the appropriate location in the interrupt vector table. at this point, a jump instruction to the appropriate isr is required. in the event of a motor control peripheral interrupt, the opera- tion is slightly different. for any of the eleven peripheral inter- rupts, the interrupt controller automatically jumps to location 0x0004 in the interrupt vector table. in addition, the required vector address (between 0x0030 and 0x0058) associated with the particular interrupt source is placed in the picvector register of the pic block. code loaded at location 0x0004 by the monitor on reset subsequently performs a jump from loca- tion 0x0004 to the address specified in the picvector regis- ter. this operation with the picvector register results in a slightly longer latency associated with processing any of the peripheral interrupts, as compared with the latency of the inter- nal dsp core interrupts. the code located at location 0x0004 by the monitor on reset is as follows: 0x0004: dm (i4_save) = i4; i4 = dm (picvector); jump (i4 ); the default code for each of the motor control peripherals is: i4 = dm (i4_save); rti; note that this default restores i4 to its value before the inter- rupt. the user should replace the rti with a jump to their isr. the put_vector rom subroutine can be used to replace the rti with the jump. the pic block manages the sequencing of the eleven motor control peripheral interrupts. in the case of multiple simulta- neous interrupts, the pic will load the picvector register with the vector address of the highest priority pending interrupt. the contents of the picvector register will remain fixed until read by the dsp. this action is performed by the default dsp code at location 0x0004. the pic block only asserts a new interrupt after the picvector register has been read. for other settings of mmap and bmode the user must cor- rectly configure the vector table. system controller modectrl register the modectrl register controls three important features of the admc401. it internally configures the sport1 pins for boot loading and uart debugging. dedicated bits in the modectrl register also control the operating mode of the pwm generation unit (single or double update mode) and the operating mode of the auxiliary pwm generation unit (indepen- dent or offset mode). two bits of the modectrl register control the internal con- figuration of the sport1 pins as illustrated in figure 34. bit 4 (dr1sel) selects which of the two external receive pins (dr1a or dr1b) is connected to the internal data receive port of the dsp core. clearing bit 4 selects the dr1a pin, whereas setting bit 4 selects the dr1b pin. following reset, bit 4 is cleared so that dr1a is selected. dsp core dr1a dr1b tfs1 rfs1/ srom modectrl (5 4) uarten dr1sel dt1 dr1 tfs1 rfs1 fl1 admc401 dt1 sclk1 sclk1 figure 34. internal multiplexing of sport1 pins bit 5 (uarten) of the modectrl register is used to select between uart and sport mode of sport1. setting the uarten bit connects dr1a to the rfs1 input which allows sport1 to be used as a uart port. additionally, the internal fl1 flag of the dsp core is connected to the rfs1/ srom pin of the admc401, to be used as a reset for the external serial
rev. b admc401 C44C rom or e 2 prom. clearing the uarten bit selects sport mode, so that sport1 is configured in a manner identical to the standard serial ports of the adsp-21xx family. following reset, the uarten bit is cleared so that sport mode is selected. bit 6 of the modectrl register is used to select between single update and double update operating modes of the pwm generation unit. clearing this bit selects single update mode, while setting it selects double update mode. following reset, this bit is cleared so that single update mode is the default configuration. bit 8 of the modectrl register is used to select between independent and offset operating modes of the auxiliary pwm unit. clearing this bit selects offset mode, while setting it selects independent mode. following reset, this bit is cleared so that offset mode is the default configuration. sysstat register the sysstat register provides various status information of the admc401, such as the state of the pwmtrip pin, the state of the watchdog flag, the state of the pwmpol pin and phase of the pwm bit 0 indicates the state of the pwmtrip pin such that the bit is set if pwmtrip is hi and cleared if the pin is lo. similarly, bit 2 indicates the state of the pwmpol pin such that the bit is set if pwmpol is hi (active high pwm selected) and cleared if the pin is lo (active low pwm selected). bit 1 is used to indicate if a watchdog timer timeout has oc- curred. this bit is set following a watchdog timeout and can be read on reset to determine if the reset is a normal power-on reset or due to a watchdog trip. bit 3 of the sysstat register is used to identify the half cycle of operation of the pwm generation unit. during the first half cycle, when the internal pwm timer is decrementing, this bit is cleared. during the second half cycle, this bit is set while the timer is incrementing. system control registers the configuration of the modectrl and sysstat register is shown at the end of the data sheet. peripheral and dsp core registers the address, name, type, used bits and reset value of all of the peripheral registers of the admc401 are given in table viii. similarly, the dsp core registers of the admc401 are tabu- lated in table ix.
admc401 C45C rev. b table viii. peripheral register map of the admc401 address name type bits reset value function 0x2000C0x2007 reserved 0x2008 pwmtm r/w [15 . . . 0] 0x0000 pwm period register 0x2009 pwmdt r/w [9 . . . 0] 0x0000 pwm deadtime register 0x200a pwmpd r/w [9 . . . 0] 0x0000 pwm pulse deletion register 0x200b pwmgate r/w [9 . . . 0] 0x000 pwm chopping control 0x200c pwmcha r/w [15 . . . 0] 0x0000 pwm channel a duty cycle control 0x200d pwmchb r/w [15 . . . 0] 0x0000 pwm channel b duty cycle control 0x200e pwmchc r/w [15 . . . 0] 0x0000 pwm channel c duty cycle control 0x200f pwmseg r/w [8 . . . 0] 0x000 pwm crossover and output enable 0x2010 auxch0 r/w [7 . . . 0] 0x00 aux. pwm channel 0 duty cycle 0x2011 auxch1 r/w [7 . . . 0] 0x00 aux. pwm channel 1 duty cycle 0x2012 auxtm0 r/w [7 . . . 0] 0xff aux. pwm channel 0 period 0x2013 auxtm1 r/w [7 . . . 0] 0xff aux. pwm channel 1 period 0x2014 reserved 0x2015 modectrl r/w [8, 6 . . . 4] 0x000 mode control register 0x2016 sysstat r [3 . . . 0] system status register 0x2017 reserved 0x2018 wdtimer r/w [15 . . . 0] watchdog timer register 0x2019C0x201b reserved 0x201c picvector r [15 . . . 0] peripheral interrupt address 0x201d picmask r/w [10 . . . 0] 0x000 peripheral interrupt mask register 0x201eC0x201f reserved 0x2020 eiucnt r/w [15 . . . 0] 0x0000 position count value 0x2021 eiumaxcnt r/w [15 . . . 0] 0x0000 maximum eiucnt value 0x2022 eiustat r [7 . . . 0] eiu status register 0x2023 eiuctrl r/w [8 . . . 0] 0x000 eiu control register 0x2024 eiuperiod r/w [15 . . . 0] 0x0000 eiu loop timer period register 0x2025 eiuscale r/w [7 . . . 0] 0x00 eiu loop timer scale register 0x2026 eiutimer r/w [15 . . . 0] 0x0000 eiu loop timer register 0x2027 eetcnt r [15 . . . 0] 0x0000 latched copy of eiucnt 0x2028 eiufilter r/w [5 . . . 0] 0x00 eiu filter control register 0x2029 eizlatch r [15 . . . 0] eiz latch register 0x202a eislatch r [15 . . . 0] eis latch register 0x202bC0x202f reserved 0x2030 adc0 r [15 . . . 0] adc0 data register 0x2031 adc1 r [15 . . . 0] adc1 data register 0x2032 adc2 r [15 . . . 0] adc2 data register 0x2033 adc3 r [15 . . . 0] adc3 data register 0x2034 adc4 r [15 . . . 0] adc4 data register 0x2035 adc5 r [15 . . . 0] adc5 data register 0x2036 adc6 r [15 . . . 0] adc6 data register 0x2037 adc7 r [15 . . . 0] adc7 data register 0x2038 adcctrl r/w [4 . . . 3,0] 0x00 adc control register 0x2039 adcstat r [4 . . . 0] adc status register 0x203a reserved 0x203b adcxtra r [15 . . . 0] extra adc data register 0x203c adcotr r [7 . . . 0] adc out of range register 0x203dC0x203f reserved 0x2040 piolevel r/w [11 . . . 0] 0x000 pio interrupt select 0x2041 piomode r/w [11 . . . 0] 0x000 pio interrupt edge/level select 0x2042 piopwm r/w [11 . . . 0] 0xfff pio pwmtrip enable register 0x2043 reserved 0x2044 piodir r/w [11 . . . 0] 0x000 pio direction control 0x2045 piodata r/w [11 . . . 0] pio data register
rev. b admc401 C46C address name type bits reset value function 0x2046 piointen r/w [11 ...4] 0x000 pio interrupt enable 0x2047 pioflag r [11 ...4] pio interrupt flag (pio4 to pio11) 0x2048C0x204f reserved 0x2050 etua0 r [15 ...0] event a captureCchannel 0 0x2051 etub0 r [15 ...0] event b captureCchannel 0 0x2052 etuaa0 r [15 ...0] event aa captureCchannel 0 0x2053 etua1 r [15 ...0] event a captureCchannel 1 0x2054 etub1 r [15 ...0] event b captureCchannel 1 0x2055 etuaa1 r [15 ...0] event aa captureCchannel 1 0x2056 etutime r [15 ...0] etu timer v alue 0x2057C0x205b reserved 0x205c etuconfig r/w [7 . . . 0] 0x00 etu configuration register 0x205d etudivide r/w [15 ...0] 0x0000 etu clock divide register 0x205e etustat r [1 . . . 0] etu status register 0x205f etuctrl r/w [1 . . . 0] 0x0 etu control register 0x2060 pwmsyncwt r/w [7 . . . 0] 0x27 pwmsync width control 0x2061 pwmswt r/w [0] 0x0 pwm software trip 0x2062C0x206f reserved 0x2070 eetn r/w [7 . . . 0] 0x00 eet pulse decimator register 0x2071 eetdiv r/w [15 ...0] 0x0000 eet clock divider register 0x2072 eetdeltat r [15 ...0] 0x0000 eet delta timer register 0x2073 eett r [15 ...0] 0x0000 eet timer period register 0x2074 eetstat r [0] 0x0 eet status register 0x2075C0x23ff reserved table ix. dsp core register map of the admc401 address name type bits function 0x3fff syscntl r/w [15 . . . 0] system control register 0x3ffe memwait r/w [15 . . . 0] memory wait state control 0x3ffd tperiod r/w [15 . . . 0] interval timer period register 0x3ffc tcount r/w [15 ...0 interval timer count register 0x3ffb tscale r/w [7 . . . 0] interval timer scale register 0x3ffa sport0_rx_words1 r/w [15 . . . 0] sport0 mutlichannel word 1 receive 0x3ff9 sport0_rx_words0 r/w [15 . . . 0] sport0 mutlichannel word 0 receive 0x3ff8 sport0_tx_words1 r/w [15 . . . 0] sport0 mutlichannel word 1 transmit 0x3ff7 sport0_tx_words0 r/w [15 . . . 0] sport0 mutlichannel word 0 transmit 0x3ff6 sport0_ctrl_reg r/w [15 . . . 0] sport0 control register 0x3ff5 sport0_sclkdiv r/w [15 . . . 0] sport0 clock divide register 0x3ff4 sport0_rfsdiv r/w [15 . . . 0] sport0 receive frame sync divide 0x3ff3 sport0_autobuf_ctrl r/w [15 . . . 0] sport0 autobuffer control register 0x3ff2 sport1_ctrl_reg r/w [15 . . . 0] sport1 control register 0x3ff1 sport1_sclkdiv r/w [15 . . . 0] sport1 clock divide register 0x3ff0 sport1_rfsdiv r/w [15 . . . 0] sport1 receive frame sync divide 0x3fef sport1_autobuf_ctrl r/w [15 . . . 0] sport1 autobuffer control register
admc401 C47C rev. b 0 0 0 0 0 0 0 0 0 0 dm (0x2038) convert start adcctrl (r/w) 1 = external (convst) 0 = internal (pwmsync) adcotr (r) dm (0x203c) 0 = in range 1 = out of range adc0 (r) adc1 (r) adc2 (r) adc3 (r) adc4 (r) adc5 (r) adc6 (r) adc7 (r) adcxtra(r) dm (0x2030) dm (0x2031) dm (0x2032) dm (0x2033) dm (0x2034) dm (0x2035) dm (0x2036) dm (0x2037) dm (0x203b) dm (0x2039) adcstat (r) 1514131211109876543210 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1514131211109876543210 1514131211109876543210 0 0 0 0 adc data adc0 otr adc1 otr adc3 otr adc2 otr adc7 otr adc6 otr adc4 otr adc5 otr 0 = in range 1 = out of range 0 00 = simultaneous sampling 01 = sequential sampling 10 = offset calibration 11 = gain calibration adc mode adc0 & adc4 adc1 & adc5 adc3 & adc7 adc2 & adc6 0 = data registers not valid 1 = data registers valid adcxtra otr 0 = in range 1 = out of range 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 35. structure of registers of the admc401 default bit values are shown; if no value is shown, the bit field is undefined at reset. reserved bits are shown on a gray fiel dthese bits should always be written as shown.
rev. b admc401 C48C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000 000 00 0 pwmtm (r/w) dm (0x2008) pwmcha (r/w) pwmchb (r/w) pwmchc (r/w) dm (0x200c) dm (0x200d) dm (0x200e) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 = disable 0 = enable ch enable cl enable bh enable bl enable ah enable al enable ah/al crossover bh/bl crossover ch/cl crossover dm (0x200f) pwmseg (r/w) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0100111 0 pwmsyncwt (r/w) dm (0x2060) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 pwmswt (r/w) dm (0x2061) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000 000 00 0 pwmdt (r/w) dm (0x2009) pwmgate (r/w) dm (0x200b) gdclk 1 = enable 0 = disable low-side chopping high-side chopping 1 = enable 0 = disable 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000 00 0 pwmpd (r/w) dm (0x200a) 000 00 0 0 0 0 000 0 0 0 000 000 000 00 0 000 000 00 0 0 0 000 15 14 13 12 11 10 9 8 76 54 3210 0000000 00 0 0 0 0 000 15 14 13 12 11 10 9 8 76 54 3210 0000000 00 0 0 0 0 000 0 0 figure 36. structure of registers of admc401 default bit values are shown; if no value is shown, the bit field is undefined at reset. reserved bits are shown on a gray fiel dthese bits should always be written as shown.
admc401 C49C rev. b default bit values are shown; if no value is shown, the bit field is undefined at reset. reserved bits are shown on a gray fiel dthese bits should always be written as shown. 0 0 0 0 0 0 dm (0x2023) eiuctrl (r/w) first zero marker 1 = received 0 = not received eiu count error 1 = error 0 = no error eiu count direction 1 = up 0 = down eiu state 1 = not initialized 0 = initialized dm (0x2022) eiustat (r) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 eiuscale (r/w) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 eiucnt (r/w) eiumaxcnt (r/w) eiuperiod (r/w) eiutimer (r/w) eetcnt (r) dm (0x2020) dm (0x2021) dm (0x2024) dm (0x2026) dm (0x2027) dm (0x2025) eis state eiz state eib state 1 = hi 0 = lo direction reverse 1 = swap eia and eib 0 = do not swap eia/eib zero marker 1 = use for reset 0 = do not use single north marker mode 1 = enable 0 = disable 1 = zero marker 0 = registration 1 = enable 0 = disable frequency & direction mode eia state 0 0 0 1 = enable 0 = disable eiu error monitoring eis latch definition eiz latch definition enable eiu loop timer eet latch definition 1 = eiutimer timeout 0 = eiucnt read 1 = enable 0 = disable 1 = zero marker 0 = registration 0000 00 00 0000 00 00 0000 00 0 figure 37. structure of registers of admc401
rev. b admc401 C50C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 = no overflow 1 = overflow eetstat(r) dm (0x2074) eet overflow 0 0 0 0 0 0 dm (0x2028) eiufilter (r/w) dm (0x2070) eetn (r/w) dm (0x2029) eizlatch (r) eislatch (r) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 eetdiv (r/w) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 encoder filter clock divide value dm (0x202a) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dm (0x2071) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 eetdeltat (r) eett (r) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm (0x2072) dm (0x2073) figure 38. structure of registers of admc401 default bit values are shown; if no value is shown, the bit field is undefined at reset. reserved bits are shown on a gray fiel dthese bits should always be written as shown.
admc401 C51C rev. b piolevel (r/w) dm (0x2040) 0 = falling edge (piomode = 0) = active low (piomode = 1) 1 = rising edge (piomode = 0) = active high (piomode = 1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 dm (0x2041) 0 = edge sensitive 1 = level sensitive piomode (r/w) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 dm (0x2042) 0 = pwm trip disable 1 = pwm trip enable piopwm (r/w) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 11 1 1 11 1 1 1 dm (0x2044) 0 = input 1 = output piodir (r/w) 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 pioflag (r) dm (0x2047) 0 = no interrupt 1 = interrupt flagged dm (0x2046) piointen (r/w) 0 = interrupt disable 1 = interrupt enable dm (0x2045) 0 = lo level 1 = hi level piodata (r/w) 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 figure 39. structure of registers of admc401 default bit values are shown; if no value is shown, the bit field is undefined at reset. reserved bits are shown on a gray fiel d these bits should always be written as shown.
rev. b admc401 C52C etuctrl (r/w) dm (0x205e) etu0 0 = do not capture 1 = start capture dm (0x205d) etudivide (r/w) dm (0x2050) dm (0x2056) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm (0x205c) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 etuconfig (r/w) etu1 mode 0 = single shot 1 = free-running etu1 interrupt 0 = next event a 1 = event b etu1 event b 0 = falling edge 1 = rising edge etu1 event a 0 = falling edge 1 = rising edge etu0 event a 0 = falling edge 1 = rising edge etu0 event b 0 = falling edge 1 = rising edge etu0 interrupt 0 = next event a 1 = event b etu1 mode 0 = single shot 1 = free-running etua0 (r) etub0 (r) etuaa0 (r) etua1 (r) etub1 (r) etuaa1 (r) etutime (r) etu1 0 = do not capture 1 = start capture etustat (r) dm (0x205e) etu0 0 = not captured 1 = sequence capture etu1 0 = not captured 1 = sequence captured 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 40. structure of registers of admc401 default bit values are shown; if no value is shown, the bit field is undefined at reset. reserved bits are shown on a gray fiel dthese bits should always be written as shown.
admc401 C53C rev. b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000 00 00 0 dm (0x2011) adc end of conversion pwmsync eiu loop timer timeout pio4 - pio11 interrupt eiu count error interrupt dm (0x201d) picmask (r/w) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000 0 dm (0x2012) 15 14 13 12 11 10 9 876543210 dm (0x2013) 0 = disable interrupt (mask) 1 = enable interrupt pwm trip interrupt pio3 interrupt pio2 interrupt pio1 interrupt pio0 interrupt etu interrupt 1 1 1 1 1 1 1 1 00 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000 00 00 0 auxch0 (r/w) dm (0x2010) 1 1 1 1 1 1 1 1 t on, aux0 = 2 auxch0 t ck auxtm0 (r/w) auxtm1 (r/w) t aux1 = 2 auxch1 t ck t on, aux0 = 2 (auxtm0+1) t ck t aux1 = 2 (auxtm1+1) t ck in independent mode t offset = 2 (auxtm1+1) t ck in offset mode auxch1 (r/w) 0000 0 00 0 0000 0 00 0 0000 0 00 0 0000 0 00 0 0 00 00 figure 41. structure of registers of admc401 default bit values are shown; if no value is shown, the bit field is undefined at reset. reserved bits are shown on a gray fiel d these bits should always be written as shown.
rev. b admc401 C54C modectrl (r/w) dm (0x2015) data receive select 1 = dr1b 0 = dr1a 1 = uart mode 0 = sport mode sport1 mode sysstat (r) dm (0x2016) 1 = hi 0 = lo 1 = watchdog trip 0 = no watchdog trip pwmtrip pin state watchdog flag pwmpol pin state 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 pwm phase flag 1 = second half cycle 0 = first half cycle pwm mode 1 = double update 0 = single update 0 auxiliary pwm mode 1 = independent 0 = offset 1 = hi => active hi 0 = lo => active lo 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 figure 42. structure of registers of admc401 default bit values are shown; if no value is shown, the bit field is undefined at reset. reserved bits are shown on a gray fiel dthese bits should always be written as shown.
admc401 C55C rev. b timer sport1 receive or irq0 sport1 transmit or irq1 software 0 software 1 sport0 receive sport0 transmit irq2 irq2 sport0 transmit sport0 receive software1 software 0 sport1 transmit or irq1 sport1 receive or irq0 timer interrupt force interrupt clear ifc (r/w) 9876543210 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 000 irq0 sensitivity irq1 sensitivity irq2 sensitivity interrupt nesting 1 = enable, 0 = disable 0 icntl (r/w) 1 = edge 0 = level 43210 10 11 12 13 14 15 9876543210 irq2 hip write hip read sport0 transmit sport0 receive imask (r/w) dsp register 1 = enable, 0 = disable 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 timer irq0 or sport1 receive irq1 or sport1 transmit software 0 software 1 dsp register dsp register figure 43. structure of registers of admc401 default bit values are shown; if no value is shown, the bit field is undefined at reset. reserved bits are shown on a gray fiel dthese bits should always be written as shown.
rev. b admc401 C56C dm (0x3ffc) tperiod (r/w) tcount (r/w) tscale (r/w) dm (0x3ffd) dm (0x3ffb) 1514131211109876543210 0 0 0 0 0 0 00 sstat (r) pc stack empty pc stack overflow count stack empty count stack overflow status stack empty status stack overflow loop stack empty loop stack overflow 76543210 1 0 1 0 1 0 1 0 mstat (r/w) 6543210 0 0 0 0 0 0 0 dsp register data register bank select 0 = primary, 1 = secondary bit reverse mode enable (dag1) alu overflow latch mode enable ar saturation mode enable mac resu placement 0 = fractional,lt 1 = interger timer enable go mode enable syscntl (r/w) pwait program memory wait states 1514131211109876543210 bpage boot page select bwait boot wait states bforce boot force bit sport0 enable 1 = enable, 0 = disabled 1 0 1 0 0 0 0 0 1 11 1 1 0 0 0 dm (0x3fff) sport1 enable 1 = enable, 0 = disabled sport1 configure 1 = serial port 0 = fi, fo, irq0, irq1, sclk az alu result zero an alu result negative av alu overflow ac alu carry as alu x input sign aq alu quotient mv mac overflow ss shifter input sign 76543210 astat (r/w) 0 0 0 0 0 0 0 0 dsp register dsp register figure 44 structure of registers of admc401 default bit values are shown; if no value is shown, the bit field is undefined at reset. reserved bits are shown on a gray fiel dthese bits should always be written as shown.
admc401 C57C rev. b 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sport0_rx_words1 (r/w) 1 = channel enable 0 = channel ignored dm (0x3ffa) 15 14 13 12 11 10 9 8 7 6543210 sport0_rx_words0 (r/w) dm (0x3ff9) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sport0_tx_words1 (r/w) 1 = channel enable 0 = channel ignored dm (0x3ff8) 15 14 13 12 11 10 9 8 7 6543210 sport0_tx_words0 (r/w) dm (0x3ff7) memwait (r/w) dwait4 dwait0 dwait1 dwait2 dwait3 rom enable 1 = enable 0 = disable 1 1 1 1 1 1 1 0 1 11 1 1 1 1 1 1514131211109876543210 note: in standalone mode (mmap = bmode = 1) the rom monitor writes 0x8000 to this register. dm (0x3ffe) multichannel enable mce iinternal serial clock generation isclk receive frame sync required rfsr receive frame sync width rfsw multi channel frame delay mfd only if multichannel mode enabled ) transmit frame sync required tfsr transmit frame sync width tfsw slen serial word length dtype data format 00 = right justify, zero-filled unused msbs 01 = right justify, sign extend into unused msbs 10 = compand using -law 11 = compand using a-law itfs internal transmit frame sync enable (or mcl multichannel length; 1 = 32 words, 0 = 24 words only if multichannel mode enabled ) invrfs iinvert receive frame sync invtfs invert transmit frame sync (or invtdv invert transmit data valid only if multichannel mode enabled ) irfs internal receive frame sync enable sport0_ctrl_reg (r/w) 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 1514131211109876543210 dm (0x3ff6) figure 45. structure of registers of admc401 default bit values are shown; if no value is shown, the bit field is undefined at reset. reserved bits are shown on a gray fiel dthese bits should always be written as shown.
rev. b admc401 C58C sport0_autobuf_ctrl (r/w) 1514131211109876543210 0 0 0 0 00 rbuf receive autobuffering enable tbuf transmit autobuffering enable rmreg receive autobuffer m register rireg receive autobuffer i register clkodis clkout disable control bit biasrnd mac biased rounding control bit tireg transmit autobuffer i register tmreg transmit autobuffer mregister dm (0x3ff3) sport0_sclkdiv (r/w) sport0_rfsdiv (r/w) 1514131211109876543210 1514131211109876543210 dm (0x3ff4) dm (0x3ff5) figure 46. structure of registers of admc401 default bit values are shown; if no value is shown, the bit field is undefined at reset. reserved bits are shown on a gray fiel dthese bits should always be written as shown.
admc401 C59C rev. b sport1_sclkdiv (r/w) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm (0x3ff1) sport1_rfsdiv (r/w) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm (0x3ff0) rbuf receive autobuffer enable tbuf transmit autobuffer enable rmreg receive m register rireg receive i register tmreg transmit m register tireg transmit i register xtaldelay 4096 cycle delay enable 1 = delay, 0 = no delay pdforce powerdown force pucr powerup context reset enable 1 = soft reset (context clear), 0 = resume execution sport1_autobuf_ctrl (r/w) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm (0x3fef) 0000 00 sport1_ctrl_reg (r/w) flag out (read only) iinternal serial clock generation isclk receive frame sync required rfsr receive frame sync width rfsw transmit frame sync required tfsr transmit frame sync width tfsw itfs internal transmit frame sync enable slen serial word length dtype data format 00 = right justify, zero-filled unused msbs 01 = right justify, sign extend into unused msbs 10 = compand using -law 11 = compand using a-law 0 0 0 0 0 0 0 0 00 0 0 0 0 0 1514131211109876543210 invrfs iinvert receive frame sync invtfs invert transmit frame sync irfs internal receive frame sync enable dm (0x3ff2) figure 47. structure of registers of admc401 default bit values are shown; if no value is shown, the bit field is undefined at reset. reserved bits are shown on a gray fiel dthese bits should always be written as shown.
C60C c3491bC1.5C6/00 (rev. b) 00108 printed in u.s.a. rev. b admc401 144-lead plastic thin quad flatpack (lqfp) st-144 1 36 37 73 72 108 144 109 top view (pins down) 0.787 (20.00) bsc sq 0.866 (22.00) bsc sq 0.020 (0.50) bsc 0.011 (0.27) 0.009 (0.22) 0.007 (0.17) seating plane 0.063 (1.60) max 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) 0.006 (0.15) 0.002 (0.05) 0.057 (1.45) 0.053 (1.40) 0.048 ( 1.35 ) 0.003 (0.08) max outline dimensions dimensions shown in inches and (mm). only dimensions in mm are accurate. the inch equivalents are approximations rounded to three decimal places. only the mm values are recommended for use in pcb layout.

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